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In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation...
FPGA-based neural-networks typically leave performance on the table because the DSP resources run at less than a third of the peak clock rate. This paper presents a processing array architected to consistently achieve timing closure at 100% of the peak DSP clock rate with standard FPGA tools. In the HDL design environment, our processing array operates at the peak DSP clock rates on Xilinx UltraScale...
The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single-voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant...
At present, APD (Avalanche Photo Diode) arrays LIDAR (Light Detection and Ranging) has been broadly accepted as an important means to obtain 3D (Three Dimensional) data. A new method of a scalable adaptive N × N channel communication system is introduced in the paper, which is aimed at improving the transmission rate of APD array LIDAR data. This paper presents the research on multi-channel communication...
In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.
Latent Dirichlet allocation (LDA) based topic inference is a data classification method, that is used efficiently for extremely large data sets. However, the processing time is very large due to the serial computational behavior of the Markov Chain Monte Carlo method used for the topic inference. We propose a pipelined hardware architecture and memory allocation scheme to accelerate LDA using parallel...
A wireless system-on-chip with integrated antenna, power harvesting and biosensors is presented that is small enough, 200µm × 200µm × 100µm, to allow painless injection. Small device size is enabled by: a 13µm × 20µm 1nA current reference; optical clock recovery; low voltage inverting dc-dc to enable use of higher quantum efficiency diodes; on-chip resonant 2.4GHz antenna; and array scanning reader...
The vertically parallel method and structures for calculating maximum and minimum values in one-dimensional and two-dimensional arrays have been developed. Developed structures have been implemented using FPGA. Parameters of the structures have been estimated.
Application code and data size have increased manifold in designs created these days, increasing the usage of embedded non-volatile memory (NVM) inside Automotive SOCs. Embedded NVM provides better security, SOC specific customization, and better integration to other SOC components. It also interacts with many critical modules, like Power Management Controller (PMC), Reset-sequencing State control...
Cool mega-array (CMA) is a kind of coarse grained reconfigurable architecture (CGRA) which has shown its ability of ultra low-power computation. However, as CMA completely eliminates clock trees and registers, the performance improvement has been limited. In this paper, we introduce a variable pipeline structure to CMA with the minimum essential registers to provide more wide trade-off between performance...
This paper presents VLSI design for sound-source localization by computing time difference of arrival (TDOA). Real-time computation yet few logic element consumption are targeted for this architecture. This system supports to recognize sound direction in 3 dimensional space by utilizing 4 sound sensors. In order to determine sound direction, we propose efficient cross-correlation method for TDOA computation...
This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC2) concept based on memory architecture for data-intensive (imaging, …) and secure (cryptography, …) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed...
Key-value stores (KVS) become critical in many applications because of the data explosion recently. There is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access...
We propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First,...
Phased array and MIMO (Multiple Input Multiple Output) radar systems are being developed with greater number of channels to achieve more flexibility, speed and range. Each channel contains either an ADC (Analog to Digital Converter) — for a receiver channel — or a DAC (Digital to Analog Converter) — for a transmission channel. In such large array, the channels need to be time synchronized as precisely...
We been developing a micro spectrometer with embedded system customizable for high sensitive 64 pixels QDs-QW photodetectors linear array. Based on silicon substrate through silicon via (TSV) technology, the readout circuit chip and the photodetector linear array have been packaged on 2.5D/3D integration. The high-speed data acquisition and processing analysis unit system have designed and optimize...
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write...
Conventional set-associative data cache accesses waste energy since tag and data arrays of several ways are simultaneously accessed to sustain pipeline speed. Different access techniques to avoid activating all cache ways have been previously proposed in an effort to reduce energy usage. However, a problem that many of these access techniques have in common is that they need to access different cache...
Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory...
Modern digital systems, which involve high data computations, suffer from high memory access latency; thus, latency becomes a core issue in the performance enhancement of these advance digital machines. Different factors are behind the high latency of advance digital systems. Approaches like array binding and allocation, code rewriting, and others are adopted to reduce the overall latency of these...
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