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Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms...
Aèsiraci-Networks-on-Chip are vulnerable to a variety of manufacturing and design factors making them susceptible to disparate faults that cause corrupted message transfer or even catastrophic system failures, due to the central position of the NoC in the system. Therefore, a NoC system should be fault-tolerant to transient malfunctions or permanent physical damages. The terminology of fault tolerant...
In this paper the applicability of a fault tolerance synchronization algorithm is presented through data packet headers. Packet headers provide indicts for networking equipment on what must be done and in the case of real-time persistent routed sessions, these are a concise guideline on how to tune each parameter. Real-time sessions are transmitted with connection oriented protocols and need a constant...
Future applications will require processors with many cores communicating through a regular interconnection network. As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system life time. In order to ensure the reliability of network-on-chip (NoC) under the faulty circumstance,...
The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative...
In this paper, we propose an adaptive routing algorithm for vertically partially connected 3D NoCs to (1) overcome failures in vertical links, and (2) find the nearest available vertical link for rerouting of packets. To track the position of each vertical link and distance to the other nodes, the proposed routing algorithm, named Advertiser Elevator, indexes each vertical link and implements a mechanism...
With the increasing device scaling in the semiconductor technology, the necessity for designing robust and efficient Networks-on-Chip (NoCs) is more pronounced. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. In this paper, a dynamically reconfigurable...
Recently, applications' demands for the network become more multifaceted. Highly functional application-to- application communication services such as bandwidth aggregation, fault tolerant communication, and delay/disruption tolerant networking (DTN) were developed independently in the network layer, the transport layer, and the application layer. As a result, protocol layering has become complicated...
A flow-based model of fault-tolerant routing with path protection has been improved. In the course of the improvement, when the fault-tolerant routing problem was presented in optimization form, an optimality criterion has been formulated, which contains the conditions for path protection when it is possible to implement both single path and multipath routing strategies. The novelty of the proposed...
Kademlia is a decentralized overlay network, up to now mainly used for highly scalable file sharing applications. Due to its distributed nature, it is free from single points of failure. Communication can happen over redundant network paths, which makes information distribution with Kademlia resilient against failing nodes and attacks. In this paper, we simulate Kademlia networks with varying parameters...
This paper proposes a new method to compute alternate routes for multiple fault tolerance on Dynamic WDM Optical Networks. The method allows to obtain all the paths that replace the primary routes affected by one or several failures. Additional paths, called secondary routes, are used to keep each user connected to the network, including cases where multiple simultaneous link failures occur. The method...
Today, with the rapid development of information technology in all areas of life, a large amount of information is created every second. In recent years, many network topologies have been proposed to find the most effective communication method. The folded hypercube is one of those networks, which is a variant of the hypercube, which is one of the most popular topologies for interconnection networks...
The locally twisted cube provides a prospective topology suitable for interconnection networks of the massively parallel systems. A routing algorithm is proposed in this paper that tolerates faulty vertices in locally twisted cubes based on two kinds of routing probabilities. A computer experiment is also conducted to verify the performance of our algorithm.
Datacenter networks (DCNs) play an important role in supporting cloud computing and Internet-based services. The cost and power consumption of a DCN grow rapidly with the increases of network scale and bandwidth requirement. The cost, complexity and efficiency of a DCN are determined by several design factors including the topology, addressing and routing. In this paper, we propose a simple and cost-effective...
Alternative architecture of neural network of self-routing analog-to-digital converter is presented in this article. The main difference of this architecture is multilayer ring topology use to keep hardware costs down of neural network assemblage. Mathematical model of basic measuring neuron is given in view of applied topology. The number of basic measuring neurons can be reduced by means of offered...
Rapid scaling of transistor gate sizes has significantly increased the density of on-chip integrations and paved the way for many-core systems-on-chip with highly improved performances. The design of the interconnection network of these complex systems is a critical one and the network-on-chip is now the accepted efficient interconnect for such large core arrays. An unfortunate adverse effect of technology...
In this paper for the first time the mathematical model and the two-level method of fault-tolerant inter-domain routing in telecommunications networks was presented. The novelty of the model is its decomposed representation and formulation the inter-area interworking conditions. The implementation of these conditions guaranteed the connectivity of calculated inter-area paths. The research of the proposed...
Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high assurance real-time systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. All possible effects of hardware errors must be taken into account and the resulting system must be predictable, even in the presence of errors. In this paper,...
Fault tolerance is a challenging requirement in virtualized data centers. While distributed layer 2 routing TRILL-like protocols are robust and scalable, they still lack efficiency upon a link failure. In this paper, we propose a hybrid architecture that achieves the best tradeoff between efficiency of centralized architectures and robustness of distributed ones. This architecture is based on a centralized...
In today's super system scenario the computation effectiveness is obtained from multiple processors which are connected to themselves and to their memory modules through multistage interconnection networks (MIN) So performability of these multistage interconnection networks (MIN) Plays vital role in effective and efficient processing of these super systems. In this paper performance of these MIN namely...
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