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Development of semiconductor process makes devices have smaller area, lower power, and reduced wire connections. To achieve this purpose, macro placement plays an important role in the design flow. In this paper, we present a routability-driven macro placement algorithm considering pins location to optimized scaled routing congestion and macro placement area. By considering pins location, reclassify...
Test Compression ratios are currently stalled at 100–200X. A new 2-dimensional physically-aware sequential Compressor-Decompressor design addresses the severe wiring congestion as well as the test coverage droop and pattern spike at the highest compression ratios. Results on some commonly used industrial designs shows a 2X reduction in routing overhead and congestion associated with Test Compression...
Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this...
As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. The latter makes them available to everyone in need of the immense computing...
Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly...
Achieving optimal floor-plans during the physical synthesis flow is an iterative and resource intensive process and its quality has a significant impact on subsequent synthesis stages in terms of runtime and quality of results. This problem intensifies due the abundance of macros in advance technology nodes which poses challenges in the physical design flow, especially in the floor-plan stage. It...
Hierarchical routing resources play vital role in FPGA routing. Better routability options can be obtained using segmented approach of wires thus enabling routing optimization. Source and sink logic blocks can be connected via wire segments such that the overall wire length and switching transistors inside the switch box can be saved over an extent. This paper presents an experimental approach of...
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
High performance chip design is always a hot topic in integrated circuit (IC) field. Clock design plays a critical role in improving chip performance and affecting power consumption. The regular clock layout has always been the ideal way to improve the timing of results. In this paper, we propose a symmetrical clock tree synthesis algorithm for top-level design, including tree architecture planning,...
In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs...
This article investigates pin accessibility problem of standard cells designed with a sub-20nm technology. The 15nm open cell library from NanGate and three of its variants with a reduced number of access points per pin based on FreePDK15 are used for our study. Our experiments show that a standard cell library is viable when the number of access points per pin is not less than three.
Wide wire sizes are often used in clock trees to improve timing characteristics and reduce electromigration effects. Recent research suggests the attractiveness of wide wires is affected by the forbidden pitch issues in the lithography of sub-20nm technologies. Parallel wiring is a recently proposed technique to get around these lithography issues in the routing stage of the ASIC design flow. Routing...
The path search problem is very common in computing. One of its applications is in the VLSI routing. Since most of the path search algorithms used today are old, their evaluation took place in out of date scenarios, such as small 2D grid graphs. Thus, this work presents some path search algorithms, as well as an experiment comparing them in a scenario similar to detailed routing of integrated circuits...
End cutting 1D layout process is a promising candidate for sub-10nm process nodes. To be correctly manufactured, any pair of end cuts must be either merged/aligned or apart from each other with at least a minimum distance. This constraint adversely affects the manufacturability, especially when the end cuts have to be solely printed with the conventional lithography technology. To improve the manufacturability,...
The wire-length of vertically stacked ICs plays a vital role. The wire-length is minimized by using differential evolutionary algorithms withIBM Benchmark inputs. Moreover this wire length is minimized with the respect to the length of the Through Silicon via (TSVs). As a result, the wire-length has been minimized using this algorithm with various parameters. Experimental result shows that the total...
This paper presents an alternative fat-wire routing approach for differential bipolar high-speed designs. The proposed solution obtains parallel routing and well balanced capacitive load of the fully differential signaling. In contrast to other approaches, the proposed flow is optimized for complex bipolar CML/ECL standard cell designs and technology options with few available routing layers. It enables...
Networks-on-chip (NoC) has been proven to satisfy different on-chip communication requirements in terms of costs, performance, and reliabilities. This has been proven true especially for spiking neural network (SNN) with its high multicast communication demands. However, metal-wires that form the foundation for regular NoCs face a set of challenges since metal-wires have been stretched to their physical...
Line-end cut process has been used to create very fine metal wires in sub-14nm technology. Cut patterns split regular line patterns into a number of wire segments with some segments being used as actual routing wires. In sub-7nm technology, cuts are smaller than optical resolution limit, and a directed self-assembly lithography with multiple patterning (MP-DSAL) is considered as a patterning solution...
The design of capacitor structures have great impact on capacitance density, parasitic capacitance, routability, and matching quality of capacitor network in a SAR ADC, which may affect power, performance, and area of the whole data converter. Most of the recent studies focused on common-centroid placement and routing optimization of the capacitor network. Only few of them investigated the structures...
In Deep sub-micron design level, interconnect plays an important role in VLSI circuit designs. Traditional interconnects are facing several challenges such as delay and power dissipation. Graphene nanoribbons (GNRs) have been found to be potential alternative for both transistors and interconnects due to its outstanding electrical and thermal properties. The construction of minimum cost global routing...
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