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In converters possessing multiple distributed controllers the synchronization of and the communication between the various controllers are important topics requiring careful consideration. The controllers should be able to transmit data and commands to each other so that different control modes can be selected, reference values updated, parameters shared and so forth. Synchronization is important...
FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. The recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration...
In this paper we prove lower and matching upper bounds for the number of servers required to implement a regular shared register that tolerates unsynchronized Mobile Byzantine failures. We consider the strongest model of Mobile Byzantine failures to date: agents are moved arbitrarily by an omniscient adversary from a server to another in order to deviate their computation in an unforeseen manner....
A central processing unit (CPU) and peripheral devices are discussed for which all data processing and data transfer is uniquely time tagged using a timestamp generated by the embedded processing system master clock. The Time Aware Processor (TAP) introduces time into the processor computing language to relate data to temporal events, including the processors own internal functions.
In this paper, we present our solution to simulate home automation networks on a functional level in our research project on self-organizing home automation network nodes. We simulate the nodes with our hardware-software co-simulator, based on the virtual machine QEMU and the SystemC hardware simulator. The Virtual Distributed Ethernet suite is used to simulate several hardware-software co-simulators...
Asynchronous circuits are interesting alternatives for implementing ultra-low power systems but they are more challenging to design. This work provides methods for designers to specify, verify, and implement self-timed pipelines. The connection of standard primitives allows specifying a control circuit. A method to derive a Petri net based model of this circuit is presented. The modeled transactions...
Synchronization using flip-flop chains imposes a latency of a few clock cycles when transferring data and control signals between clock domains. We propose a design scheme that avoids this latency by performing synchronization as part of state/data computations while guaranteeing that metastability is contained and its effects tolerated (with an acceptable failure probability). We present a theoretical...
In this paper, a 14-bit 300-MHz current-steering digital-to-analog converter with output transimpedance stage is presented. The drain-source voltages of MOS devices in real current sources could be stabilized within a limited small range due to the feedback of opamp in transimpedance stage. The nonlinear distortion caused by current sources could thus be suppressed. The simulated INL and DNL are below...
NVIDIA GPUDirect is a family of technologiesaimed at optimizing data movement among GPUs (P2P) orbetween GPUs and third-party devices (RDMA). GPUDirectAsync, introduced in CUDA 8.0, is a new addition whichallows direct synchronization between GPU and third partydevices. For example, Async allows an NVIDIA GPU to directlytrigger and poll for completion of communication operationsqueued to an InfiniBand...
Data movement is increasingly becoming the bottleneck of both performance and energy efficiency in modern computation. Until recently, it was the case that there is limited freedom for communication optimization on GPUs, as conventional GPUs only provide two types of methods for inter-thread communication: using shared memory or global memory. However, a new warp shuffle instruction has been introduced...
A partial parallel architecture for LDPC (Low Density Parity Check Code) decoder is proposed. The overall architecture is based on MIMD (Multiple Instruction Stream Multiple Data Stream), the internal calculation unit is based on SIMD (single instruction Stream multiple data Stream). The processor uses the programmable method to realize the NMS (normalized minimum sum) decoding algorithm, can get...
Modern SoC / NoC chips often provide GeneralPurpose I/O (GPIO) pins for connecting devices that are not directly integrated within the chip. Timing accurate control of devices connected to GPIO is often required within embedded real-time systems — ie. I/O operations should occur at exact times, with minimal error, neither being significantly early or late. This is difficult to achieve due to the latencies...
Redundant Multi-Threading (RMT) provides a potentially low cost mechanism to increase GPU reliability by replicating computation at the thread level. Prior work has shown that RMT's high performance overhead stems not only from executing redundant threads, but also from the synchronization overhead between the original and redundant threads. The overhead of inter-thread synchronization can be especially...
As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make...
SoC design trends show increasing integration of special-purpose, third-party hardware blocks to accelerate diverse types of computation. These accelerator blocks interact with each other in unexpected ways when integrated into a complex, accelerator-rich SoC. In this work we propose a novel solution that guides verification engineers to the high-priority accelerator interaction scenarios during RTL...
This paper present an optimal register alignment for minimization of clock switching scheme in Mesochronous operation. In Mesochronous operation, data are processed in one or more processing clocks based on executing instructions. In this scheme, a delayed clock pulse is allotted for each instruction in the processing unit. Due to different clock frequencies for different instructions, the overhead...
USB 2.0 Specifications are used with ASIC & their Embedded USB 2.0 support in order to enhance the USB 2.0 Peripheral development. UTMI is basically USB 2.0 Transceiver Interface which is added to library of ASIC vendors. Peripherals and IP Vendors can create their design with great ease in association with USB 2.0 interfaces, thereby minimizing time & risk of their development cycle. In this...
Most of modern verification architects use randomness supported by system verilog (SV) to enable defining a generic path for a test to follow. This generic path stresses on a subset of features, and allows randomization to explore corners in depth. Setting up such test case requires a well-defined stimulus generation methodology that consumes less time to cover all the corner-cases. Moreover, Off-the-shelf...
The integration of mixed signal circuits in Systems on Chip is a trend in modern systems and applications with important challenges. In particular, the simulation of this kind of systems is a very time-consuming process that is becoming more and more complex due to the size of current designs. This paper describes a HW/SW co-simulation environment for mixed-signal circuits. The analog components are...
The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) at Darmstadt, Germany. The challenge in CBM experiment is to measure the particles generated in nuclear collisions with unprecedented precision and statistics. To capture the data from each collision a highly time synchronized fault tolerant self-triggered electronics is required for Data...
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