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Terahertz (THz) plasmonic field effect transistor sensors have emerged as prime contenders for applications in THz and sub-THz communications, biomedical sensing, and imaging. Noise is one of the most important factors determining their performance. We show that the conventional approach of using thermal noise of the device impedance for predicting the sensor performance is inadequate because it ignores...
The high frequency voltage oscillation on the DC/DC gate driver of a H-bridge created during the turn-off intervals of the power switches has critical impact on component reliability and control quality. This noise can propagate freely in the low power plane to other functional circuits of the converter due to the performance degradation of EMI filter in high frequency range above 30MHz. In this paper,...
This letter presents an RF noise model for AlGaN/GaN HEMTs. The model is based on active line approach and concept of two ports linear noise theory. Short channel effects such as channel length modulation and velocity saturation are considered in the model. The noise generated from the pinch off region is taken into account as well. Some of FET noise parameters are calculated and experimentally verified.
A generally accepted noise model of a FET without gate leakage current requires the knowledge of the elements of an equivalent circuit and three temperatures: physical temperature Ta and equivalent temperatures, Tg of intrinsic gate resistance and Td of drain conductance. Experimental confirmations have been published for III-V FETs and HEMTs and also for MOSFETs. There is, however, still a disagreement...
In this paper, we aim to present a surface potential based model for GaN High Electron Mobility Transistors. The analytical model is computationally efficient and can be accurately used for DC and RF predictions. It includes various effects of velocity saturation, access region resistance, temperature, gate current and noise.
In this paper, we designed Schmitt trigger using CMOS low power design technique at 45nm technology. With the advancement of technology, different parameters have been calculated and analyzed to determine the performance of the circuit. With the change in technology, the aspect ratio of transistor sizing, variation in parameters also takes place. Different techniques are applied for the reduction...
In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.
We present fully self-consistent small signal and microscopic noise simulations of a nanoscale double-gate nMOSFET by a semi-classical and deterministic approach. We show how such a system of Poisson, Schrödinger and Boltzmann equations can be used to self-consistently determine several key quantities relevant to circuit designers.
In high efficiency and high temperature industrial applications, wide bandgap semiconductor devices, such as: Gallium Nitride (GaN) and Silicon Carbide (SiC), are getting great attention due to their outstanding performance. However, a false turn-on phenomenon can be produced by the switching noise because wide bandgap devices have low threshold voltage. Consequently, the efficiency of a switched-mode...
Reliability issues of MOSFETs such as bias temperature instability (BTI), random telegraph noise (RTN), and stress-induced leakage current (SILC), are linked to the trapping of charges in oxides. Even though the chemical structure of these oxide defects is still the subject of debate, detailed studies of these reliability phenomena have shown that their physical behavior can be successfully described...
This paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density...
This paper proposes an efficient envelope delta-sigma based transmitter architecture with gate bias modulation for modern wireless communication systems. Using this architecture, envelope varying signals are converted to constant envelope signals. The constant envelope phase signal is up-converted and amplified utilizing high efficiency power amplifier, while the two level delta-sigma modulated envelope...
In modern computers information is processed through binary switches, usually realized with transistors, i.e. Microelectronic devices. Thus binary switches represent a paradigmatic example of "small scale physical systems" employed in the processing of information. In the last forty years the semiconductor industry has been driven by its ability to scale down the size of the CMOS devices,...
Random Telegraph Noise (RTN) has become dominant with transistor rapid scaling in recent years. We simulate RTN-induced frequency fluctuation of Ring Oscillators (ROs) using a circuit-level simulator to replicate measurement results from previous works. Consequently, we can predict dependences of frequency fluctuation on operating voltages, number of ROs stages, gate widths, and body biases.
A high spatiotemporal resolution, wireline operation-based, in-vivo neural recording system is presented. The proposed system allows selecting 64 channels from 512 recording sites. The neural signals from the 64 selected sites are amplified, filtered, and finally multiplexed in the time domain. The output signals of each multiplexer are buffered, converted to the current domain, and then transferred...
Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed...
The root cause of degradation and failure in nanoscale logic and memory devices originates from discrete defects (traps) that are created in the ultra-thin dielectrics during fabrication (process-induced) and / or voltage and temperature stress (stress-induced). In order to probe the chemistry of every discrete trap in terms of its bond state, charge state, physical location, region of influence,...
The power, speed, area and energy constraints are the major user concerns, when it comes to choosing the appropriate logic family for new applications. This paper introduces customizable logic families and presents a comparative analysis of such logic families, to enable the user to make a robust choice. Energy efficiency has been identified as one of the most required features for modern electronic...
A fully integrated low power LNA is implemented using 65-nm RF CMOS technology for 2.14-GHz band. By taking the advantage of higher transition frequency of recent technologies, transistors are biased in the moderate inversion region and this permitted scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversion led to the development of a low power...
The performance of logic function could be affected significantly by the noise effect as the dimension of CMOS devices scales to nanometers. Thus, many pertinent researches about noise-tolerant logic gate have received growing attention. Considering the randomness as the noise's nature, probabilistic-based approach proves better noise-immunity and three design schemes with the technique of Markov...
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