The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide...
CMOS and nano-electromechanical (NEM) hybrid reconfigurable logic (RL) circuits are implemented by using monolithic three-dimensional (M3D) integration process. Their operation and feasibility are discussed based on simulation and experimental results.
Data retention and power consumption during the hold mode of operation of a SRAM cell is of high importance. Hence, there is a need for a cell design that improves Static Noise Margin (SNM) and consumes low static power. This paper presents a Schmitt-Trigger (ST) based Single-Ended 11T SRAM cell that uses dual-threshold CMOS technology which exhibits high read and hold SNM and consumes low power during...
The performance limitations of the single cell FAMOS transistor have hindered the development of high speed MOS EPROM's that can match Bipolar PROMs for speed. Previous approaches to high speed MOS EPROMS have centered around a 4-T 11 I or a 2-T cell with It's inherent die area disadvantage and, hence, resulted in their manufacturable densities being limited to under 64K.
Introduction. Fast CMOS ECL interfaces offer important savings in off-chip delays for high speed CMOS SRAM, especially for sub-10 ns accesses in high speed large system applications. Asynchronous CMOS differential amplifier circuits in a 1 μm 5V technology [1] can meet the joint requirement of high speed and light tolerances needed for ECL receivers [2J.
Stochastic processes are ubiquitous and the stochastic differential equation is a formal setting to analyse dynamic circuits in noisy environments. Initially, Norbert Wiener developed stochastic integral to prove the nondifferentiability of the Brownian motion with probability one. Later, it was utilized by Kiyoshi ItΣ to construct stochastic differential rules. This paper discusses two Theorems....
This paper presents a CMOS high linearity power amplifier for LTE application. We use inverter circuits and t second harmonic control to improve the linearity. This circuit will be processed with TSMC 0.18 µm technology. The simulation result shows that the circuit exhibited a power gain of 25.9 dB, an input return loss less than - 20.2/20.9dB, the PAE is about 35%/31.2% and the output power is about...
We are developing artificial retinas using poly-Si thin-film transistors (TFTs), which is suitable for the epiretinal implant on the curved human eyeballs. In this study, we confirmed stimulus performance of poly-Si TFTs in in-vitro experiment for artificial retinas. It is found that correct output waveforms are observed using a CMOS inverter and ring oscillator. This means the stimulus performance...
In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capacitor circuits. However, the cascade-inverter architecture of ring amplifier may suffer from undesirable oscillation which has a great impact on transient stability. This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
It has been made clear that the presence of hot carriers triggers a series of physical processes that affects the FD-SOI and FinFET device characteristics under normal circuit operation. These effects cumulatively build up over prolonged periods, causing the circuit to age with time, resulting in performance degradations that may eventually lead to circuit failure. In this paper we tackle with the...
This paper investigates the substitution of CMOS or near-threshold CMOS with Charge Recovery Logic (CRL) in applications where energy is thermally harvested. By doing so, it is possible to eliminate the bulky DC/DC stage needed to provide the supply voltage for CMOS operation. Instead, a simple LC-tank oscillator is used to generate a power-clock suitable for CRL operation. Simulation results of a...
This paper describes the implementation of a new architecture to multiply signals with time-mode representations. The exponential relationship between voltage and time in an RC circuit is utilized to implement time-mode logarithmic and exponential functions needed to realize a time-mode analog of the translinear principle. Addition of time-mode variables is achieved through the natural progression...
RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
Although QCA (Quantum-dot Cellular Automata) is a promising nanotechnology to replace CMOS (Complementary Metal-Oxide-Semiconductor), it has several known reliability problems. Consequently, the design of robust QCA circuits is a mandatory step towards the consolidation of this new technology. This paper presents a novel methodology for error analysis of QCA circuits based on deterministic and random...
We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors...
This paper focuses on Signal Integrity (SI) and Power Integrity (PI) integration characteristic research. The voltage fluctuation across the power supply of Integrity Circuit (IC) is called Simultaneous Switching Noise (SSN). The research emphasizes on the SSN generated from packages since the switching of I/O in chip. A CMOS inverter chip [1] is designed because of the simplicity of the model, the...
The interest for ultra-low power integrated circuits in the recent past has guided the research community to establish the proposal of several adiabatic logic circuits in which the energy stored can be efficiently recycled. Many of these architectures suffer from problems like glitch & huge number of transistors as compared to conventional CMOS, which stop them to be used in practical scenario...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.