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In this paper, we investigate the combinatorial design of a new class of One-Step Majority-Logic Decodable (OSMLD) codes, based on Balanced Incomplete Block Designs of type Oval, which are derived from finite geometry. We show that the constructed OSMLD codes provides high rates in addition to good correction capacities. Simulation results shows that the proposed codes converge well under iterative...
This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH code remarkably enhances the hard-decision-based error-correcting performance to defer the energy-consuming memorysensing operations for generating the soft-decision values, which are necessary to prolong the lifetime of flash memories...
Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy...
This work proposes a decoder implementation for high-rate generalized concatenated (GC) codes. The proposed codes are well suited for error correction in flash memories for high reliability data storage. The GC codes are constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. The extended BCH codes enable high-rate GC codes. Moreover, the decoder...
Since physical unclonable functions (PUFs) are considered for various security applications such as authentication and key generation, the robustness of PUFs is vital. In prior works, various error correction codes, such as Bose-Chaudhuri-Hocquenghem (BCH) codes, were used to improve the robustness of PUFs. In this paper, we use polar codes, a new family of error correction codes, to improve the robustness...
In this work, we give the first construction of high-rate locally list-recoverable codes. List-recovery has been an extremely useful building block in coding theory, and our motivation is to use these codes as such a building block. In particular, our construction gives the first capacity-achieving locally list-decodable codes (over constant-sized alphabet); the first capacity achieving} globally...
In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed...
In this paper, we interpret the polar codes based on Plotkin construction perspective. We briefly review the rate allocation for component codes of Plotkin codes and the construction of polar codes based on Gaussian approximation. Then, we show that the recursively constructed Plotkin codes can be a class of polar codes. And also, the polar codes are a class of Plotkin code having minimum threshold.
The possibility of describing the encoding and decoding procedures Bose-Chaudhuri-Hocquenghem codes using the summation operations modulo 2 is researched. This allows you to simplify these procedures and improve efficiency by correcting the error of the triplicate. There identified coding equations and triangular match tables: the syndrome — the distortion of the position.
In satellite on-board computers, memories are one of the components that need protection against radiation. Their effects can cause several types of errors like: Single Event Upsets (SEUs) that affect a bit of memory, Multiple-Cell Upsets (MCU), which corrupt several bits, and Single Event Functional Interrupt (SEFI) in control circuits, which can cause malfunction of the entire memory chip. This...
Increasing soft error rate and decreasing technological nodes sizes pave a way for Error Correcting Codes (ECC) widespread use in embedded systems. Depending on application safety goals and acceptable performance and area overhead, different codes can be selected. The goal of this paper is to investigate the efficiency and expediency of two of the most prominent ECC codes, Hamming and Hsiao, in the...
Conventional iterative timing recovery is developed based on the widely used assumption of Additive White Gaussian noise (AWGN) interference. The Gaussian-based approach is excellent for timing recovery over AWGN channel with matched filtering approach but does not perform well in the presence of non-Gaussian noise. Overall performance of the conventional iterative timing recovery with matched filtering...
In this paper we propose a robust representation of a digital signal based on error correction codes. For each frame of the signal (N successive samples) a binary decomposition, as a (successive power 2) weighted sum of binary vectors, is first considered. Then, each binary vector is projected into the set of codewords of a corresponding block code. The codes are designed so that their correction...
In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2. Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length...
The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated...
The main aspect considered in this paper is a comparison of interleaver sizes for convolutional and low-density parity-check codes (LDPC) employed for 100 Gbps wireless communication at 240 GHz with parallel sequence spread spectrum (PSSS). Interleavers required for PSSS-15 and convolutional codes are larger in silicon area than a complete Reed-Solomon decoder. Thus, convolutional codes are not recommended...
The task of the definition of an a priori unknown Error Correcting code is one of the major tasks for governmental radio control authorities. In particular, the case of the choice of the most probable ECC from the predefined ECCs set. The SA-method (Syndromes analysis method) is suggested to solve the issue. This method is based on the sequences syndrome analysis. Here are given basic results, which...
The decoding problem is addressed in this paper for the scenario that convolutional codes are employed at the source node of the network with linear or convolutional network coding for error correction. Since network errors may disperse or neutralize due to network coding, decoding cannot be done at sink nodes merely based on the minimum Hamming distance between the received and sent sequence. Source...
Several types of insertion/deletion/substitution error correction codings have been proposed for channels with imperfect synchronization. Most of the conventional coding schemes assume insertion/deletion errors of bit granularity, while in some applications, e.g. bit patterned media recording, insertion/deletion errors occur as a result of accumulation of small synchronization errors. This paper considers...
In this paper, we study lattice coding for Rician fading wireless channels. This is motivated in particular by preliminary studies suggesting the Rician fading model for millimeter-wavelength wireless communications. We restrict to lattice codes arising from rotations of Zn, and to a single-input single-output (SISO) channel. We observe that several lattice design criteria suggest the optimality of...
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