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Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 108/mm2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances...
Impact of advanced technologies on the design and structure of multicore architectures is presented in this paper. More specifically, the power consumption and design complexity walls are examined leading to a “conquer-and- divide” strategy based on multicore partitioning and specialization. We then show how 3D stacking, Monolithic 3D integration and BEOL NVM can be associated to build new, simplified...
CoolCube™ is a monolithic 3D technology which has the potential to solve the interconnection density limitation of the existing TSV-based 3D integration processes. Since the active devices are fabricated on extremely this die substrates, heat dissipation has been pointed as a potential showstopper issue for this emerging technology. This work provides a comparative study of the thermal performance...
In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar...
In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.
While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ...
This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements...
Scaling race towards aggressive nodes is getting more and more difficult as dimensions are getting close to the atoms ones. New solutions have to be investigated to find new ways of scaling while keeping the Moore's law benefits in terms of area, power, performance and cost. These solutions should leverage on existing technologies for reducing their development cost by proposing new usages. Also,...
In this paper, we propose to analyze FDSOI technology suitability for IoT applications and more specifically for autonomous Wireless Sensor Nodes. As IoT applications are extremely diversified there is a strong need for flexible solutions not only at design and architectural level but also at technological level. Moreover, as most of those systems are recovering their energy from the environment,...
3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets...
In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is achieved through similar steps as required by 2D designs: pre clock tree synthesis (including placement), clock tree synthesis and routing; to which we added a folding step in order to emulate the 3D placement. Routing of both tiers in parallel...
Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential...
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology...
FPGA have always taken benefit of the most advanced technology nodes for offering better performance than CPU and better time-to-market than ASSP. However, with the slow-down of technologies and its exponentially increasing cost, FPGA race towards better integration is nowadays compromised. One alternative path to scaling is to go 3D. This promising solution can offer scaling at a lower cost while...
This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation...
In order to understand the dynamics of large neural networks, where information is widely distributed over thousands of cells, one of today's challenges is to successfully monitor the simultaneous activity of as many neurons as possible. This is made possible by using the Micro-Electrode Array (MEA) technology allowing neural cell culture and/or tissue slice experimentation in vitro. Thanks to development...
In order to understand the dynamics of large neural networks, where information is widely distributed over thousands of cells, one of today's challenges is to successfully record the simultaneous activities of as many neurons as possible. This is made possible by using microelectrodes arrays (MEA) positioned in contact with the neural tissue. Thanks to microelectronics’ microfabrication technologies,...
A 16 channel front-end IC dedicated to small animal positron emission tomography has been developed for cross-strip CdTe detectors. Each channel, designed to handle up to 20 pF detector capacitance, includes both low voltage (2 nV/Hz1/2) and low current (40 fA/Hz1/2) noise, high bandwidth (50 MHz at 20 pF detector capacitance) current amplifier with a gain of 100 for a power consumption of 4.7 mW...
In this paper, we present two circuits designed for pulse readout of a semiconductor PET system: a fast low noise low power front-end preamplifier/shaper, and a processing circuit performing time tagging, energy measurement and digital interfacing with the data acquisition system. Considerations on noise, speed and power consumption are discussed.
A 64 channels CMOS chip dedicated to in-vitro simultaneous recording and stimulation of neurons using microelectrode arrays has been developed. It includes, for each channel, a low noise, variable gain (10, 75 or 750), 0.08 Hz-3 kHz bandwidth measurement path with unity-gain for lower frequencies to allow measurement of the electrochemical potential. A snapshot style Sample & Hold circuitry allows...
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