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Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for a high speed serial interface to be used in automotive Electronic Control Units. The transmitter has been designed in a standard 28 nm technology and features feed-forward equalization (FFE) with 8 taps (1 pre- and 6 post-cursors), whose strength is programmable with 16 discretization steps. It is...
This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given...
A fractional-N digital PLL with injection locking and a fractional resolution higher than the native resolution given by the number of ring oscillator stages occupies 0.042 mm2 in 40 nm CMOS technology. It features a 400-to-1200 MHz digitally-controlled ring oscillator and in injection-locked mode, it tracks temperature and voltage changes by applying Bang-Bang phase detection re-alignment to the...
In the field of digital PLLs, there is a trend to find alternatives to time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2–4]. Architectures based on bang-bang phase detectors are very attractive for their low-jitter, low-power capabilities, but are limited to integer-N operation by nature. Solutions that...
This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and reduces accumulated jitter substantially (by a factor of 8 in our implementation) with no penalty to EMI reduction or to period jitter. As a key advantage, the proposed design allows...
This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background...
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