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A finite element model which contains one sixth of the IGBT module based on a real test chip of IGBT module is established to investigate the temperature and stress distribution of different shape bonding wire. The finite element (FE) analysis which coupled electro-thermal and thermal-mechanical are conducted using commercial software ABAQUS. The thermal performance and stress distribution of IGBT...
As the demand of power converter for higher power density is increasing, bonding wire failure of IGBT module becomes more severe. Accordingly, it is of great significance to investigate the reliability of bonding wire under operating condition for improving the reliability of IGBT module. In this paper, the finite element model of IGBT module was established, and a two-step indirect coupling electro-thermal-mechanical...
Insulated gate bipolar transistor (IGBT) operates at high current, high power and repeated shock current conditions. Joule heating induced during high current conditions, subsequently raising the temperature of the IGBT module. In this paper, we carried out the DC power cycling test with the 200 A current condition. The temperature distribution and the temperature change process of the whole IGBT...
Thermal cycling reliability test and finite element analysis have been conducted for plastic ball grid array assembly with Sn63Pb37 solder. Based on the thermal cycling test results, a two-parameter Weibull distribution model was used to determine the characteristic time to failure of plastic ball grid array assembly. Besides, cross-sectioning and optical microscope examination were utilized to identify...
In order to achieve the packages with much higher performance, more I/Os, lower profile and lighter weight, the thickness of silicon wafer has been decreased dramatically in recent years, but which degrades the strength of thinned wafer. In this paper, three-point bending test was adopted to evaluate the thinned wafer fracture strength, and the impacts of back-grinding process parameters on the wafer...
As the demand expanding for high electrical performance, high pin count and low cost, the copper pillar bump packaging has been extensively used in recent years. However, the drawback is that copper pillar bump can introduce high stress, especially on low-k chip. In this paper, finite element method was adopted to optimize the structure of copper pillar bump, aiming at relieving the stress of low-k...
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