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A new switched capacitor (SC) converter for powering miniature sensor systems with wide load current and output voltage ranges is proposed in this paper. By adopting a multiple-ratio SC stage and reconfigurable stage interconnect scheme, the proposed converter offers fine granularity of conversion ratios, which improves efficiency for light load operation. The multiple-leaf structure for switch size...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved...
This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog convertor (DAC) by 91% compared with the conventional approach. By utilizing the comparator as a voltage-to-time converter (VTC) with...
Over the past decade, a large family of spintronic devices has been proposed as candidates for replacing CMOS for future digital logic circuits. Using the recently developed modular approach framework, we investigate and identify the physical bottlenecks and engineering challenges facing current spintronic devices. We then evaluate how systematic advancements in material properties and device design...
IR-drop induced false capture failures and test clock stretch are severe problems in at-speed scan testing. We propose a new method to efficiently and accurately identify these problems. For the first time, our approach considers the additional dynamic power caused by glitches, the spatial and temporal distribution of all toggles, and their impact on both logic paths and the clock tree without time-consuming...
Detailed knowledge of a circuit’s timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit’s inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls...
This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction...
An excessive switching activity during the functional capture cycles of scan-based tests can lead to overtesting of delay faults. Low-power test generation procedures that address this issue consider the switching activity of the fault-free circuit. This paper observes that an excessive switching activity in a faulty circuit can also affect the test application process. In particular, we show that...
The influence of technological and circuit parameters variations on the combinational circuit elements delay increases with the transistor size reduction. Delay uncertainty comes from the parameter values dispersion; therefore, it is critical to analyze the possible delay variance. This paper presents the solution to problems of complex digital circuits performance analysis with the presence of the...
A novel method for removing multiple switching at the edges of digital signals based on a comparator with dynamic hysteresis is presented. The proposed concept is analytically investigated and a CMOS circuit is designed based on the obtained results. Simulations with Spectre simulator demonstrate its correct operation.
This paper presents fast, low loss, and low noise gate driver for Silicon-Carbide (SiC) MOSFETs. We proposed gate boost circuit to reduce switching losses and switching delay time without increasing switching noise. The proposed gate driver makes it possible to improve converters efficiency or enhance power density of converters. SiC power devices have attracted huge interest as next generation power...
A research on the emission charge of a BaTiO3 surface flashover trigger device and of pseudospark switch (PSS) and its trigger characteristics are presented in this paper. The experimental results have been found that BaTiO3 surface flashover trigger device has more excellent electron emission characteristics than that of ZnO. The electron emission charge Qe of BaTiO3 surface flashover trigger device...
A soft-transition converter is proposed which offers significant merits over traditional second order boost converter. The Boost converter provides higher voltage level at lower duty ratios and the ripple at input and output is also reduced. The Zero-Voltage Transition (ZVT) cell which is also incorporated into the circuit provides further advantages in terms of reduction of switching losses for all...
A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated...
This paper presents a low-voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). An input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive-DAC (CDAC). By utilizing the comparator as a voltage-to-time converter (VTC) and implementation of time-domain quantizer, the input range is detected to...
Low-power multipliers are very important for reducing energy consumption of digital processing systems. This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e. using registers and using AND gates, to assert...
This article present the design of automatic component to control room condition. The lights and fan will turn on in accordance ideal temperature workspace when there are peoples in the room and if no one in the room then the room lights and fan will not be active. This research use PIR sensor and LM35 as input, a component is developed based on FPGA device. The IP core of component is ready to fabricate,...
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising...
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