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This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
In this paper, we analyzed near-threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte...
Full Adder is one of the fastest adder used in the complex data processing to perform fast arithmetic operations. The main aim of this paper is a design of 2T XOR gate based full adder using GDI technique.2T XOR gate is an absolutely necessary primitive in the design of full adder. Intension behind a novel method of 2T XOR gate based Full adder design is to reduce power improve the speed with an optimized...
4×4 Vedic multiplier using domino logic is proposed in this paper. The designs are implemented in GPDK 90nm technology on cadence virtuoso tool using spectre simulator. Multiplication is a fundamental operation, which is widely used in many digital signal processing systems, multimedia applications, computers and many digital systems. Power and delay are two important design constraints but there...
This paper presents a 65nm ASIC based 256 NIST prime field ECC processor. To achieve high throughput, extensive pipelining techniques were applied to realize the Karatsuba-Ofman Multiplier along with enhanced NIST Reduction Formula. The processor architecture was implemented using Global Foundry 65nm Low Power (LPE) technology. The processor runs at a maximum frequency of 244 MHz and performs single...
A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into partitions, and one number is replaced by two with zeros interlaced in every other partition. Products are computed with no carries between partitions, in the time required to multiply the short partitions and add the partial sums. Component adders and multipliers can be chosen to trade off area and speed....
The advancement in IC technology is primarily attributed to the MOSFET scaling theory. As the transistor size reduced, power consumption also reduced. As the process technology reached nano-meter regime, silicon CMOS started developing Short Channel Effects which led to increased power dissipation. A trade-off arose between power-dissipation and area. Alternatives to CMOS were found to avoid the trade-off...
A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for...
This present paper, a 3 transistor XNOR gate is proposed. The proposed XNOR gate is designed using CADENCE EDA tool and simulated using the SPECTRE VIRTUOSO at 180 nm technology. The proposed results are compared with the previous existing designs in terms of power and delay. It is observed that the power consumption is reduced by 65.19 % for three transistor XNOR gate and 48.11% for eight transistor...
Previously published research works have proposed several designs for low power hybrid full adder cells and analyzed their power-delay performance against standard logic styles in various simulation environments. In this paper, a 1-bit energy efficient hybrid full adder cell has been proposed and its performance in terms of power, delay and power-delay product (PDP) has been compared with that of...
The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. In this paper, 1-bit hybrid full adder is designed using Complementary Metal Oxide Semiconductor (CMOS), transmission gate and pass transistor logic. The circuit is implemented...
Standard cell design and memory design need to be optimized for sub-threshold operation. It is interesting to revisit digital block architectures when implemented using these sub-threshold basic bricks. Out of many possible architectures for the same logic function (i.e. Multiplier), it turns out that there are optimal sub-threshold architectures.
This paper presents a noise-coupled VCO-based two-stage delta-sigma ADC, which achieves third-order noise-shaping with only one active integrator. Noise-coupling technique is applied to VCO-based quantizer to get second-order noise-shaping, used as a second stage in two-stage delta-sigma ADC to overcome the nonlinearity of the VCO. The first stage is a firstorder delta-sigma modulator with a three-bit...
Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low...
After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
Addition is the fundamental operation used in computer arithmetic circuits and CMOS adder is the basic component of these systems. This paper presents the designs of new 4-bit and 8-bit split-path Data Driven Dynamic logic (sp-D3L) ripple carry adder (RCA) circuit. Power consumption of proposed 4-bit RCA's varies from 0.69nW to 2.75nW with variation in supply voltage from 1.8V to 3.3V. Maximum output...
In this paper, a low-power high speed 4-2 compressor circuit is proposed for fast digital arithmetic integrated circuits. The 4-2 compressor has been widely employed for multiplier realizations. Based on a new exclusive OR (XOR) and exclusive NOR (XNOR) module, a 4-2 compressor circuit has been designed. Proposed circuit shows power consumption variation in the range of 718.72 pW to 3357.40 pW. Maximum...
Spin Wave Functions (SPWFs) realize computation with spin waves, offering several benefits and new features over CMOS. SPWF technology potentially opens up new directions for designing microprocessors with increased capabilities over current implementations. Towards this end, as a preliminary work an 8-bit embedded processor is explored here using SPWFs and evaluated in terms of its power, area and...
This paper proposes a 1-Bit full adder cell using Double Gate FINFET (Fin Shaped Field Effect Transistor) at 45nm CMOS technology. The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented...
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