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Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead of strict accurate computation, relaxed requirements might increase performance and reduce power consumption with a simplified or inaccurate circuit. One of the recent remarkable research efforts is the accuracy-configurable approximate adder designs, which can gracefully operate in both approximate (inaccurate)...
Approximate computing is a promising approach for low power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy configurable adder designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of these...
This paper presents architectures for user defined floating point add subtract unit with modified leading Zero Anticipator (LZA). In floating point addition unit, adder and normalization unit decides critical path delay. Predicting the shift amount before the adder output helps in reducing the delay introduced by the normalization. Most of the available algorithms are inexact in nature. They predict...
High speed multiplier designs have been the primacy for multiplier dominated applications such as wireless communications, computer applications, and image processing. In this paper a high performance fixed word length multiplier design by using recently proposed technique to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary...
Arithmetic logic units and digital signal processors widely uses adders. It is the most complicated arithmetic circuits in digital electronics. The existing adders suffer from critical path delay, area overhead and power consumption. Speculative adders are designed with variable latency that combines speculation technique along with correction methodology to attain high performance in terms of low...
Arithmetic unit design using reversible logic gate has received much attention as it reduces power dissipation with no loss of information. This paper proposes the design of 32-bit Binary Coded Decimal (BCD) addition and subtraction unit using reversible logic gates. The reversible 32 -bit BCD addition unit is designed using the following modules such as reversible 4-bit Carry Propagate unit using...
High speed multipliers are an essential component for real time multimedia applications. Majority of these applications can tolerate some amount of error in output of the multiplier and error permissible can dynamically vary within an application. This paper presents architecture for an accuracy configurable modified Booth multiplier (ACMBM) using approximate adders, whose error can be configured...
Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique...
Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable...
Multi-stage latency adders based on different prediction schemes have been proved promising to enhance the circuit performance with negligible overhead. This paper presents a novel predictor exploiting both the detection and the sequence-dependence between the successive calculations. The detection of carry-kill pattern of the input data can lower the probability of the operation with multiple clock...
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