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This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations...
The extensive improvement in the VLSI technology results in optimization of various factors, at the same time causing overhead in area, delay etc. Multipliers being the integral part of major application systems like Digital Signal Processor (DSP), Microprocessor and Application Specific Integrated Circuits (ASIC'S) plays a major role in the overall area, power consumption and performance of the processor...
A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or...
Limitations of present complementary metal oxide semiconductor (CMOS) technology are heat dissipation, power dissipation, scaling problem and performance degradation. These problems can be resolved by adopting new emerging technologies like quantum-dot cellular automata (QCA) and reversible logic technology, which provides a new horizon in low power computation. Reversible logic technology handles...
Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In the present paper,...
In this work, we have proposed an implementation of a testable reversible adder using conservative reversible logic for Spintronics based nanomagnetic logic (NML). The testable adder has the advantage that all unidirectional stuck at faults can be detected concurrently while the circuit is performing the normal operation. Further, the unidirectional faults can also be tested offline using only two...
Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not wide spread owing to the absence of a clear design methodology and the required CAD tools. In this regard, this paper presents a methodology to...
For many processing operation addition forms the basis, that is from counting to multiplication to filtering. As a result adder circuit are important therefore we have proposed design of quaternary adders such as quaternary ripple carry adder, quaternary carry look-ahead adder, quaternary carry select adder. The various quaternary adders shows power consumption of 64% less as compared to binary circuits...
Ling-carry adders that use a Ladner-Fischer parallel-prefix algorithm for carry computation are explored for quantum-dot cellular automata (QCA) nanotechnology implementations. The results derived from drawn layouts, indicate that the proposed adders outperform in terms of delay all previously reported architectures explored for QCA implementations. The delay difference is becoming bigger in favor...
In this paper, we address the design of wide-operand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end we first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss the cost and performance of each strategy. Our analysis identifies as a major direct folding drawback...
Quantum-dot cellular automata (QCA) technology is a promising alternative to CMOS technology. QCA provides a novel paradigm both for communication and computation. Meanwhile, a new challenge referred to as the “layout = timing” problem is introduced due to the unique clocking and inherent pipeline nature of “wires” in QCA. As a result, feedback is intractable in sequential circuits due to the QCA...
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