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The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact...
This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting...
Aiming at the problem of the lack of a type of ordnance equipment unit fault location method, based on UC/GUI embedded graphic user interface, designs a new detection and diagnosis system. the system function includes the self-inspection, Spare parts testing, the actual equipment testing and theory teaching. The system adopts C8051F020 MCU and S3C2440 ARM9 microprocessor, integrated application data...
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
Integrating analog-to-digital converters that utilize a phase-sensitive detector (PSADCs) are frequently used in high precision instrumentation and measurement systems. As any technical object, a PSADC is subject to faults. These faults must be detected promptly and accurately by built-in low complexity hardware. In the present work, this objective is achieved by the adoption of error-control codes...
To study or control the behavior of an actual equipment, such as a protection relay in a complex power system, real-time digital simulators can be employed in order to provide a safe and efficient environment for researchers. The goal of this paper is to investigate and verify the operation of an “actual” overcurrent protection relay in a simulated distribution system. More precisely, this work has...
This paper is devoted to a problem of on-line testing efficiency in digital components of safety-related systems taking into account their design for operation in two modes: normal and emergency. Approach to increase of on-line testing method trustworthiness in checking of approximate results is offered. Approach is based on distinguishing of the essential and inessential errors caused by faults of...
This work reports an effective test design for memory. It realizes March algorithm employing a periodic boundary cellular automata (PBCA) structure. The irreversible single length cycle attractor cellular automata (CA), selected for the design, returns correct decision on the fault in memory even if the test logic is defective. It avoids the bit by bit comparison of memory words, practiced in the...
This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize...
Growth of nanometer electronic components increases requirements to testing of the logic circuits. In frame of conventional testing becomes not enough to detect stuck-at faults at circuits' gate poles it is necessary to test timing defects. One of a convenient and popular model of timing defects is path delay faults. A technique of designing a self-checking synchronous network of Finite State Machines...
Since the introduction of the IEEE C37.20.7 standard and predecessor documents for testing switchgear under arcing fault conditions, the use of arc-resistant equipment has increased and is now the standard in many companies in the petrochemical and oil industries. Equipment designs have evolved to be more robust under fault conditions to meet the testing criteria, but there is limited knowledge of...
This paper develops a practical, cost-effective method of retrofitting existing low voltage motor control centers to reduce the arc flash energy for open door work to a much safer level. These self-extinguishing solutions are designed to reduce the arc flash energy from a calculated value in excess of 40 calories per square centimeter (cal/cm2) at an 18 inch working distance to an average tested value...
At present there is no standardized grounding method for medium voltage direct current (MVDC) shipboard power distribution systems. This paper introduces a method for selection of a maritime MVDC grounding scheme that considers technical acceptability, maintainability, reliability, safety, and feasibility. Several candidate grounding approaches and the results of the selection process are presented...
A novel 2-stage testing structure for CMOS pixel sensor (CPS) is proposed here. The test stimuli are based on applying the electrical pulses instead of light stimuli on photosensitive area, for pure electrical test. The voltage stimuli applied is generated by charge-pump phase locked loop (CP-PLL) which is used here as on-chip clock, exploiting the dual role. Existing charge-pump circuit as stimulator...
Static Random Access memory (SRAM) has a dense and regular layout structure with Bitlines (BL) and complementary Bitlines (BLN) running simultaneously along with power and ground lines. It can result in fabrication failures during wafer processing. Memory test algorithms read and write specific data in particular sequence so that maximum possible functional failures could be detected during testing...
A simulation study is conducted to model the behavior of the MOS transistor output response with a resistive defect on gate, with both DC and pulse signal inputs. Nanoprobing is performed on actual transistors in DC and pulse modes to validate the simulation. Compared to a reference transistor, a more resistive gate corresponds to a larger rise time in the dynamic pulse response, while the static...
Efficient test and diagnosis methods are required to ensure high levels of dependability of the electronic systems deployed to the market. These methods involve a trade-off in terms of accessibility to test nodes, test stimuli complexity, area overhead, and data processing that, altogether determine the impact that the involved operations have in the final cost, performance, and reliability presented...
Testing digital circuits is crucial for guaranteeing the correct and reliable functioning of electronic devices. Deriving high quality test suites to check the correctness of such devices is an important task. To estimate the quality of a test suite, a common approach is to simulate faults in a given circuit specification and to assess the fault coverage of the test suite. In this paper, we propose...
This paper presents a unique and efficient artificial neural network (ANN) based fault detection, classification and location on part of the Nigerian 132kV transmission line. The objective is to evaluate the performance of ANN based relays connected at both ends of the lines using feed-forward non-linear supervised back propagation algorithm with Levenberg-marguardt network topology. Using the PSCAD/EMTP...
In order to have proper operation of the “relay” protection devices, their behavior shall be studied and tested for different possible operational conditions. The harmonic spectrum in the supervised circuits may affect the protection functions. Harmonics can be generated in the primary circuits by faults, non-linear loads, converters, etc. Harmonics can also be induced in the secondary circuits by...
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