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This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three...
In this paper, a 60 GHz low noise amplifier (LNA) using a 130 nm SiGe BiCMOS process is designed and presented. Common emitter (CE) and cascode topologies are used in the first and second stages respectively to ensure that minimal noise figure (NF) and maximum gain are achieved. To investigate the performance of the CE in relation to the NF, the mathematical analysis of the NF of the first stage is...
Achieving large low-frequency gain together with low noise and a high unity-gain bandwidth (UGB) imposes conflicting requirement on bias currents in single stage operational transconductance amplifiers (OTA). In this work, we propose a modified biasing scheme for folded cascode OTAs to de-couple the gain versus noise/UGB trade-off. The effectiveness of proposed biasing scheme is illustrated with the...
We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification...
This paper describes an op-amp with a novel Class-AB Push-Pull output stage employing a “constant-transconductance” cell for keeping the amplifier gain-bandwidth product constant over different load conditions. A biasing scheme is also examined to define the quiescent current of the op-amp. The circuit is part of the current sensing scheme for a DC-DC Buck converter. The proposed system has been built...
Available fractional-order PIλDμ controllers introduced in the literature use discrete component realizations, where the approximations of fractional-order integration and differentiation operations is performed using appropriately configured RC networks. A novel re-configurable fractional-order PIλ controller, suitable for brake and throttle control in an autonomous vehicle, is presented in this...
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
Passive EMI filters occupy significant volume in a power converter. This work involves the study of utilizing Active EMI Filters (AEF) and Hybrid EMI Filters (HEF) to reduce the volume of passive filters. The DUT under consideration is a 30 W AC-DC converter. Since the power level less than 65 W it does not have a PFC stage. In this work, noise sensing is carried out using voltage sensing methodology...
A two-stage low-noise amplifier (LNA), designed using GlobalFoundries' 130 nm SiGe BiCMOS process technology for 56–64 GHz applications is presented in this paper. The LNA consists of two cascode stages, with inductive degeneration using short stub transmission lines with a quarter wavelength. The input matching and output matching adopt T-section matching to ensure optimal noise and input matching,...
This paper presents synthesis of analogue frequency filter with differential input and differential output terminals. The inner structure of the filter has single-ended form, i.e. filter behaves as so-called pseudo-differential circuit. Active elements of the filter are Differential Voltage Buffer (DVB) as an input stage and Modified Current Differencing Unit (MCDU) together with Modified Current...
The standardization for the fifth generation (5G) of mobile and wireless networks is at its early phase and has recently completed the first study item in Release 14. Nevertheless, there is a consensus that 5G will address the diverse service requirements of high-variety use cases. The network shall cope with such variation effectively and cost-efficiently even though the requirements can change over...
This paper presents a 28.1GHz ultra-low-power down-conversion sub-harmonic mixer (SHM). Two novel circuit topologies are proposed. First circuit introduces an AC-DC signal splitting LC-tank based on the conventional mixer. By utilizing the LC-tank, the resistor for small signal is enhanced and just one stage transistor exists between a voltage supply (VDD) and ground (GND). A Single-NMOS switch is...
Effect of resistive feedback on performance parameters of Common-Source (CS) low noise amplifier (LNA) is studied in this paper. For this purpose, an ultra low power, low noise figure (NF), high power gain (S21) low noise amplifier (LNA) for narrowband (NB) wireless applications is proposed in this paper. The LNA is designed for 2.4 GHz narrowband (NB) using 90nm CMOS process. It has a 3-dB bandwidth...
This paper presents a 300 MHz to 3 GHz Low-Noise Amplifier (LNA) with high HP3 and one of the smallest silicon area we could find. It is based on a single amplifier, where it is systematically optimized to achieve better results than more complex noise canceling topologies, thus, saving area and power consumption. A CMOS inverter with resistive feedback where transistors are self-biased in strong...
A 280 μW current-reuse, sub-threshold balun low noise amplifier (LNA) is presented for medical radio device communication (MedRadio) over the frequency range of 401- 406 MHz. An exemplary balun LNA is designed in a UMC 0.18- μm CMOS technology. The differential conversion of RF input has been procured by stacking power phase splitter (PPS) on top of the inductively degenerated common-source (IDCS)...
A new low-voltage push-pull output stage is proposed. It can be adapted for use in low-voltage two-stage or multi-stage amplifiers. A 2-stage amplifier and a 3-stage amplifier were fabricated using this output stage in a 65-nm CMOS process with threshold voltages of 0.35V for p-channel and 0.5V for n-channel devices. Silicon measurements show both the amplifiers are able to operate with a power supply...
A second harmonic mixer appropriate for direct conversion recievers is realized in 0.18 μm SiGe technology. The realized topology offers a unique mechanism to prevent LO to RF leakage, thus, suppress the DC Offset voltage due to LO self mixing. The constant current consumption of the topology provides a proper isolation of the noise mixing operation from the supply lines. Large signal analysis of...
The design procedure with the optimum performance of a Low Noise Amplifier (LNA) is presented. The noise performance, Linearity, power dissipation and high gain feature of an LNA have been qualitatively analyzed and finally an optimum LNA design topology has been tried to achieve, among possible common source (C-S) architectures with 0.13μm CMOS process. The design has been targeted on the Bluetooth...
In this paper, a fully differential low voltage folded cascode CMOS low noise amplifier for zig-bee based applications in wireless sensor networks is presented. The noise figure can be reduced by various gain enhancement techniques of folded cascode LNA. By using capacitive cross coupling technique for LNA, enhancement in trans conductance and linearity of common gate topology can be achieved. The...
The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated...
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