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Owing to the advantages of low standby power and high scalability, ReRAM technology is considered as a promising replacement for conventional DRAM in future manycore systems. In order to make ReRAM highly scalable, the memory array has to have a crossbar array structure, which needs a specific access mechanism for activating a row of memory when reading/writing a data block from/to it. This type of...
Identifying the technology trends, key patents to be aware of, the key players active in the field, the product areas that are heavily patented or scarcely addressed, and the focus of a company's competitors represent crucial aspects of developing a successful strategic plan, determining a company's freedom to make and sell their product, and focusing future research & product development efforts...
A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time...
The reliability of digital integrated circuits is becoming the primary design concern in advanced technology nodes. The accelerated transistor aging mechanisms, such as Bias Temperature Instability, reduce the noise margin of memory cells leading to increased failure rate. Traditionally, error correction codes, such as Hamming code, are widely used to detect and correct transient errors in memory...
Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes...
Energy is quickly becoming an inevitable challenge to using a large die-stacking DRAM cache. Emerging STT-RAM technology can efficiently reduce the static energy of large cache. However, STT-RAM which has high write energy and latency is not suitable to completely substitute for on-die DRAM cache. We observe that there are a large number of redundant bits written in the row buffer and futile bits...
This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC2) concept based on memory architecture for data-intensive (imaging, …) and secure (cryptography, …) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed...
The computational speed of a conventional von Neumann computer architecture is limited primarily by the data path bottleneck between the memory and the central processing unit (CPU). One solution to this problem is to eliminate the separation between the CPU and memory by moving the processor functions directly into the memory. The Database Accelerator (DBA) chip is an attempt to merge these two functions...
Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data...
We propose a novel 15-T Transmission-gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First,...
Read only memories (ROMs) serve as an important non-volatile memory in various hardware systems to store predefined data and programs. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. This paper proposes a new transformable via-programming ROM design to address the vulnerability to reverse energy attacks. Irreversible via...
The structural performance of electronic devices depends immensely on the standoff height of the components used to assemble them. The component standoff height (CSH) of electronic assemblies can be varied either by changing the settings of the reflow profile parameters or by varying the diameter of bond pad on the printed circuit board (PCB). The continued desire by electronic manufacturing industries...
Microelectrode Array (MEA), with a ring plate similar to a Petri dish, is a device used for in-vitro neuron culture and their electrophysiological signal recording. The analysis of these signals is useful for the study of neuronal network dynamics and the drug tests in pharmacological application, between others. The electric signals captured by MEA are of low amplitude and require special amplifier...
This paper reviews our recent work on Si and SiGe THz sources that generate high-power coherent radiation. Our design approach blends the optimization of device operation near or above fmax with unconventional circuit topologies and energy-efficient electromagnetic structures. Using a 130-nm SiGe HBT process (fmax=3D280 GHz), our 320-GHz transmitter produces a record radiated power (3.3 mW) and DC-to-THz...
Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose...
Noise parameter measurements of six candidate transistors for a Square Kilometer Array (SKA) low-noise amplifier (LNA) are presented. They provide reliable data in the frequency range where some low-noise transistors are inadequately characterized. The results of these measurements inform the design of an LNA for SKA1-Survey Band 2 with measured minimum noise temperature of 21 K.
The series resistance of STT-MRAM cells becomes increasingly important in deeply scaled nodes. Next to the typical scaling of width and thickness of the copper layers, barriers further reduce the cross-section of the actual copper. Moreover, at these small sizes, the resistivity of copper degrades compared to bulk copper. This paper presents a novel STT-MRAM cell design with partial source line planes,...
A 16Mpixel 3D stacked CMOS image sensor with pixel level interconnections using 4,008,960 micro bumps at a 7.6μm pitch, which set no layout restriction and causes no harm to sensor characteristics, was developed to achieve both a 16Mpixel global-shutter mode with a −180dB PLS and 2Mpixel 10000fps high speed image capturing mode.
This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1× at iso-area in 28nm FDSOI.
Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T bit cells that are significantly larger than 6T SRAM cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM cells, reducing array area by 2–5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM bit cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes...
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