The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The paper presents a continuous comparison comparator as an IP block. The comparator is developed in a standard semiconductor manufacturing process of 180 nm and can be applied in the design of system-on-a-chip devices, a dual-slope ADC in particular. This ADC can be used in the design of multimeters, digital thermometers, and other devices. The comparator is modeled in Cadence software. The result...
In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro,...
The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 0C. This work proposes an analysis of latched-comparators...
A novel non-volatile 1-bit binary comparator based on pure memristors and an 8-bit comparator based on 1T1M (1 transistor per memristor) crossbar array are proposed in this paper. The proposed comparator is sneak-path free and has short delays. It can be extended to an arbitrary N-bit comparator with 7N memristors and 7N transistors. The worst case input-to-output delay is 4.8ns. A 64-bit comparator...
This paper presents a GaN transistor half-bridge prototype with robust pulse by pulse current limiting drivers designed to turn off safely the transistor for the rest of the PWM period when the drain current exceeds the set value. The half-bridge is intended as the key part of a DC/AC converter output stage with operating frequency up to 1 MHz. The current limiting circuit is designed to meet the...
For efficient design of digital circuits operating under wide range of voltage voltages, RTN model incorporating the dependencies of both the gate area and supply voltage are required. In this paper, we characterize the delay distributions due to RTN under different supply voltages. The delay distributions are then converted to threshold voltage distributions by statistical analysis. Measurement results...
A fully synthesizable analog-like loop filter for a Low-Dropout regulator using only digital standard cells is proposed. To accommodate this, various blocks such as comparator, time-to-digital converter and charge-pumps are developed using only standard cells. The fabricated prototype in 0.13μm process occupying 0.0875mm2 provides 15mA current with minimum quiescent current of 140μA and load transient...
This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the...
A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with...
As the feature size of semiconductor technology continues to scale down, conventional synchronous circuit design methods encounter more and more design challenges, one of which is the routing of global clock trees meeting timing and power requirements. Asynchronous circuits, which do not rely on global synchronization, provide alternative opportunities to their synchronous counterparts. This paper...
The main constraints in recent trends of VLSI technology are power, area and delay. CMOS designs occupy more area and dissipate more power. Power dissipation results in heating up of an IC which directly affects the reliability and performance. Multipliers are the integral part of major application systems like Microprocessor, Digital Signal Processor (DSP) etc., so it is necessary to optimize the...
Content-addressable memory (CAM) is the hardware based particular type of memory device utilized for low power and high-speed application. CAMs are developed for precise application without sacrificing their search speed, and it is much faster than random accessmemory (RAM) in search application. CAM executes two essential functions storing and comparing. The additional circuitry during comparison...
Until now, only few researches have been reported in application of memristor in analog circuits, despite the actual fact that analog memristor switching (MRS) is more intriguing than digital memristor switching. In this research, potential application of memristor in analog circuit is explored. A programmable delay element (PDE) which consists of memristor resistance write circuit, read circuit and...
Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS...
A Look-Up Table (LUT) shows modest performance (delay and power) when used as a universal logic module (ULM) for implementing all possible combinational functions; moreover, the complete programmability of a LUT (so for all functions) incurs in a significant circuit complexity. Few approaches have been proposed by which a LUT is replaced by circuits; this is possible because in practice, the number...
This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We...
This paper presents an open-loop 28GHz 16-phase clock generator in 28nm CMOS technology. The open loop architecture is composed of 22.5° delay units and uses phase compensation to account for delay time variations. The 16-phase 28GHz clock generator consumes 14mW, leading to a power efficiency of 0.032mW/GHz/phase. The maximum phase error is 6° and the RMS phase error is 3° when the input frequency...
Continual growth in the size and functionality of FPGAs over past few years has resulted in an increasing interest in their use for high speed applications. However, the execution speed is limited by the memory access speed and the whole function is affected due to the great amount of data. This paper introduces a novel high speed and high-area efficiency MRAM-based non-volatile look-up table (nvLUT)...
Presently, the utilization of novel digital VLSI circuits increasing exponentially. Recent trends in the design of such circuits are to decrease the node capacitance and power supply requirements. Because of this fact, huge susceptibility to transient faults increases in the nano-range digital CMOS designs. We have constructed a new robust fault resistant D-latch for low power applications. We designed...
We optimize and compare the performance of synchronous and asynchronous comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.