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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
A 10-bit single-channel SAR ADC is designed in a 130nm CMOS technology. An original DAC is proposed, merging a binary-weighted structure and a C/2C topology in order to reduce overall energy consumption. A built-in calibration circuit improves the conversion accuracy. The proposed SAR ADC samples at 6.66MHz, achieving a SNDR of 49.78 dB for a 1MHz input signal (ENOB of 8 bits). The simulated INL is...
Lifetime of aluminum electrolytic capacitors is of paramount importance, since in many power electronic voltage source converter systems this capacitor type is used in the DC-link. Thermal stress is one of the most critical stressors for electrolytic capacitors leading to wear-out and failures. Therefore, methods to perform online monitoring of the hotspot temperature of capacitors would lead to beneficial...
This paper presents an AC-powered, boost-converter-based multi-segmented LED driver that maintains a high-power factor (PF) and accurate input current level, using a novel look-up table (LUT)-based digital control with background calibration and optimal switching mode selection schemes. The presented multi-segmented LED driver aims to reduce the costs of high-voltage capacitors and high-inductance...
We present a summary of the results of an intercomparison of high voltage capacitance between the National Metrology Institutes of Argentina (INTI) and Uruguay (UTE). The traveling standard was a 400 kV, 50 pF capacitor, SF6-isolated. This capacitor was calibrated in each laboratory against their own standards, comparing the results.
This paper analyzes ratio and phase displacement errors produced by commercial capacitive voltage transformers (CVT) under non-sinusoidal waveforms, as exist in power networks. As power quality measurements in high voltage systems are performed at the low voltage side, it is relevant to know the incidence of the CVT in the results. Additionally, a preliminary proposal to compensate those errors is...
This article induces the key points and test principles of the developed the digital carpet electrostatic tester, which is used to measure the electrostatic charge amount generated by the friction between the shoes and the carpet when people walking on the carpet. The design of the hand-held electrode is based on the principle of capacitor divider. The paper proposed a static calibration based on...
A CMOS digital temperature measurement technique is reported, which doesn't require an explicit reference voltage during temperature to digital conversion. Instead, one of the inputs from the sensor core serves as the reference. After eliminating the need to use an external reference, we observe at least twofold increase in temperature estimation accuracy compared to the reference based traditional...
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This...
The adoption of charge-redistribution-technique-based successive approximation register (SAR) architecture in capacitance domain has improved the performance of the digital readout circuit used for capacitive sensor applications. The direct conversion of an off-chip sensor's capacitance to a digital value requires a large implemented capacitor array. A scale factor scaling the reference voltage is...
This paper presents a calibration technique based on missing-code-detection (MCD) scheme to correct the gain error between the MSB and the LSB array in SAR ADCs with bridge-DAC structure. The MCD algorithm replaces the gain factor calculation with simple missing-codes count that significantly reduces the calibration digital overhead. It also relieves the linearity requirement of the testing signal;...
This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900...
High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200 MS/s pipeline ADC is described. A combination of a digital foreground and a digital background...
This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method...
This paper presents an all-digital background blind calibration technique for the capacitor mismatch problem in SAR ADCs. It utilizes the redundancy offered using a sub-radix-2 DAC architecture to blindly estimate the mismatch and the assigned weight for each comparator decision. The weights are estimated by building partial histogram windows for the comparator decision vectors. To remove the dependency...
Efficient and smart techniques for analog data acquisition and processing may play crucial role in the design of miniature wearable devices, meant to continuously record, process and wirelessly transmit vital physiological parameters for real time health monitoring. In this work we propose a low-power, all-analog processing unit for an MPG (magneto-plethysmograph) based wearable device, which is meant...
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning,...
The calibration of the transresistance gain of low-current dc amplifiers can be performed with the capacitance-charging method, where the calibration current is generated by a calibrated voltage ramp applied to a reference capacitor. The method is typically implemented with a purposely-built voltage source having a very low-frequency trapezoidal periodic waveform output. Here we propose a variation...
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that...
In this paper, a novel ultra-low power, programmable gain instrumentation amplifier (PG-IA) for biomedical signal processing applications is presented. The fully differential PG-IA employs a new rail-to-rail current mirror input pair with three stage indirect compensation (RR-CMI) amplifier. The proposed design improves the dc offset by implementing a fully symmetrical structure and is further reduced...
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