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This paper addresses a delay-driven layer assignment problem with consideration of via delay and coupling effect in the global routing stage. A negotiation-based framework is proposed to balance delay, congestion, and via count. Coupling capacitance is considered using a probabilistic look-up table. Finally, the proposed algorithm uses both parallel wires and wide wires to reduce wire delay. The effectiveness...
As VLSI technology shrinks to fewer tracks per standard cell, e.g., from 10-track to 7.5-track libraries (and lesser for 7nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multi-bit flip-flops or flop trays to save power creates large cells that further complicate critical design...
Routability has become a very challenging issue in a modern VLSI design flow. Many works use global routing to estimate the routability in the early design stages. However, global routing cannot accurately capture local congestion, so it is hard to detect the detailed routability issue. To more accurately estimate the detailed-routing routability, this paper presents a track-assignment-based routability...
Routability has become a challenging issue with designs scaling down. Recently, global-routing-based routing congestion estimators (GRCEs) are widely used to detect the routability problems in the early VLSI design stages. To make GRCEs fast, using parallel routing approaches to speed up GRCEs is a promising direction. However, integrating existing parallel routing approaches into a GRCE may degrade...
Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method...
A 2.5D IC provides a silicon interposer to integrate multiple dies into a package, which not only offers better performance than 2D ICs but also has lower manufacturing complexity than true 3D ICs. In an interposer, routing wires connect signals between dies or route signals from dies to the package substrate. The number of metal layers in an interposer is one of the critical factors to affect the...
Placement consists of three stages: global placement, legalization, and detailed placement (DP). Recently, most research works have concentrated on improving global placement and legalization, but innovations in DP have been rarely seen. ICCAD13 held a DP contest that formulates the emerging placement issues into a bin-utilization metric and maximum cell displacement constraint. This paper presents...
Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D...
In an attempt to develop safe and robust methods for monitoring migraineurs' brain states, we explores the feasibility of using white, red, green and blue LED lights flickering around their critical flicker fusion (CFF) frequencies as foveal visual stimuli for inducing steady-state visual evoked potentials (SSVEP) and causing discernible habituation trends. After comparing the habituation indices,...
To address the routability issue, routing congestion estimators (RCE) become essential in industrial design flow. Recently, several RCEs [1–4] based on global routing engines are developed, but they typically ignore the effects of routing on timing so that the identified routing paths may be overlong and thus impractical. To be aware of the timing issues, our proposed global-routing-based RCE obeys...
Routability has become a critical issue in VLSI design flow. To avoid producing an unroutable design, many placers [4–7] invoke global routers to get a congestion map and then move cells to reduce congestion based on this map. However, as cells move, the accuracy of the congestion map degrades, thereby affecting the effectiveness of the placer in minimizing congestions. Moreover, most global routers...
Conventional buffer insertion in timing ECO involves only minimizing the arrival time of the most critical sink in one multi-pin net and neglects the obstacles and the topology of routed wire segments, which may worsen the arrival times of other sinks and burden subsequent timing ECO. This work develops a topology-aware ECO timing optimization (TOPO) flow that comprises three phases - buffering pair...
Considering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8–11] adopt a built-in global router to estimate routing congestion. While the routability of the placement solution improves, the performance of these placers degrades. Many of these built-in global router and state-of-the-art academic global routers...
Multiple dynamic supply voltage (MDSV) provides an effective way to reduce dynamic power and is widely used in high-end or low-power designs. The challenge of routing MDSV designs is that the net in MDSV designs needs to be planned carefully to avoid electrical problems or functional failure as a long interconnect path pass through the shutdown power domains. As the first work to address the MDSV...
In order to improve pattern recognition based on partial discharge detected with ultrasonic method, repetitiveness of partial discharge(PD) in different defects are measured and 34 steady defect characteristic parameters are got from the extracted 43 characteristic parameters. Then, the 24 effective characteristic parameters are filtered as input of neural network. Finally, an improved GA-BP neural...
Layer assignment determines on which layer the wires or vias should be placed; and the assignment results influence the circuit's delay, crosstalk, and via counts. How to minimize via count and via overflow during layer assignment has received considerable attention in recent years. Traditional layer assignment to minimize via count tends to produce varying qualities of assignment results using different...
Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which...
Given the extensive study of clock skew minimization, in the ISPD 2009 Clock Network Synthesis (CNS) Contest, clock latency range (CLR) was initially minimized across multiple supply voltages under capacitance and slew constraints. CLR approximates the summation of the clock skew and the maximum source-to-sink delay variation for multiple supply voltages. This work develops an efficient three-stage...
The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wire-length estimations to a placer. This work presents two routing techniques, namely adaptive pseudorandom net-ordering routing and evolution-based rip-up and reroute using a two-stage cost function...
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