Search results for: Weixin Gai
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This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
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A 40 Gb/s PAM4 receiver with novel digital clock and data recovery (CDR) and one tap decision feedback equalizer (DFE) has been presented. Without sophisticated transition detection and selection modules, the proposed CDR utilizes three bang-bang phase detectors sampling all the transitions to detect the phase error between the data and clock, achieving larger transition density and CDR bandwidth...
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This paper presents a 65nm CMOS 6.5GHz digitally-controlled oscillator (DCO) with static and dynamic supply sensitivity of 0.00138%-fDCO/1%-VDD and 0.0071%-fDCO/1%-VDD respectively. By regulating the supply current of DCO, the proposed technique achieves high supply-noise rejection performance. In addition, the proposed DCO has a strong immunity against process and achieves satisfied performance at...
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A 10GHz analog phase interpolator (PI) in Global Foundry 65nm CMOS technology has been presented. The PI mainly consists of the quadrature clock generator (QCG) and the phase Mixer. Different from the traditional divider, the QCG produces 4-phase clocks without reducing the clock frequency. As a result, it reduces the frequency of PLL from 20GHz to 10GHz, which can largely save the power consumption...
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This paper presents a speculative architecture of a digital phase-locked loop (DPLL)-based clock and data recovery (CDR) for high-speed receiver in series links. This proposed system removes pipeline stages and reduces propagation delays, as a result, the latency of the loop decreases, which improves the loop stability and jitter tolerance without sacrificing loop bandwidth. This system can realize...
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A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
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A novel PAM4 receiver with adaptive threshold voltage, adaptive decision feedback equalizer and fixed linear equalizer has been presented. The proposed techniques enable threshold voltage to be adjusted automatically depending on data rate, signal swing and loss of channel. Consequently the receiver can be used in various situations without being manually calibrated. Adaptive decision feedback equalizer...
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Electronics Letters > 2015 > 51 > 12 > 901 - 902
A novel 10 Gbit/s source-series-terminated (SST) transmitter in 65 nm CMOS technology is presented. Different from the conventional SST transmitter with the swing fixed to the supply voltage, the proposed transmitter, employing modified SST topology with switch-based shunting legs, achieves tunable swing to provide suitable a output voltage for specific channel loss, resulting in higher power efficiency...
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Electronics Letters > 2015 > 51 > 10 > 745 - 747
An analogue equaliser with a novel digitally tuned variable degeneration resistance is realised in a 65 nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well fit the optimal conductance curve, the proposed variable degeneration resistance is exploited to achieve a wide boost range while significantly improving the linearity of the tuned boost...
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This paper presents a 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. The parallel input to the transmitter is pre-coded at low frequencies, so that the pre-emphasis tap injects different currents into the output node of the transmitter based on different level changes of the output signal. The proposed pre-emphasis suppresses overshooting and lowers power consumption. The...
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A novel half-rate source-series-terminated (SST) transmitter in 65nm bulk CMOS technology is presented in this paper. Compared to previous half-rate SST transmitters, the proposed one consists of four binary-weighted slices increasing proportionally as 1x, 2x, 4x and 8x and the range of pre-emphasis level is increased greatly by the clock-match block to adapt to different channel. The half-rate transmitter...
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This paper presents a 65-nm CMOS 40-Gb/s PAM4 transmitter with power-efficient pre-emphasis. Switchable current sources are used in the pre-emphasis tap to eliminate power wasting. The pre-emphasis tap only injects current to the output nodes upon the voltage level transition of the output signal. Current does not flow through the pre-emphasis tap when there is no transition. Simulation results show...
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A 5.4 GHz All-Digital Phase-Locked Loop (ADPLL) is presented in this paper. The ADPLL is designed in 65nm CMOS process. A 7 bit wide output swing and high linearity digital-to-analog converter (DAC) is used in this ADPLL to achieve good jitter performance. The proposed current-mode DAC with dual compensation circuits compensates the channel modulation effect. It demonstrates output swing of 1 V and...
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This paper presents a novel sub-ranging delay-line based analogue to digital converter (ADC) for DC-DC converter. The proposed ADC utilizes both rising and falling edge of the delay line to respectively perform coarse and fine quantization. A 4-bit 100MHz ADC employing the novel sub-ranging analogue-to-digital conversion was implemented in 0.18-µm CMOS process. The estimated area is approximately...
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This paper proposes a high-speed low-complexity simplified recursive degree computationless modified Euclid's (SrDCME) architecture for the Reed-Solomon Decoder. The area-efficiency of the proposed architecture is obtained by replacing the conventional systolic architecture with a recursive architecture that uses a single processing element. The hardware complexity was further reduced by merging the...
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IEEE Circuits and Systems Magazine > 2014 > 14 > 3 > 45 - 54
Electronic systems are prevalent in every field of human activity. Undergraduate education in the field of Circuits and Systems (CAS) at Peking University (PKU) is the focus of this paper. We highlight some of the practices at undergraduate level, which have been developed in an attempt to make CAS education more appealing and effective. Undergraduate students share the same curriculum in their first...
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Electronics Letters > 2014 > 50 > 24 > 1811 - 1813
A 65 nm CMOS 20 Gb/s transmitter with a low-voltage differential signalling (LVDS) driver is presented. A novel power-efficient pre-emphasis method that eliminates power wasting in conventional pre-emphasis is proposed. The input to the driver is pre-coded so that the pre-emphasis taps only inject current to the output nodes upon voltage level transition of the output signal. Current does not flow...
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A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly...
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This paper examines two kinds of bang-bang semidigital dual loop CDR architectures: 2nd-order and 3rd-order. Quantitative analysis is made in detail between the two in the presence of spread spectrum clocking (SSC) which hasn't been well studied. Moreover, a novel SSC estimator based on 3rd-order architecture is proposed to suppress the frequency-overshoot of conventional 3rd-order CDR happening at...
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A method to reduce the supply voltage sensitivity of digitally-controlled ring oscillators (DCROs) using digital current-regulated tuning is presented. By regulating the supply current of ring oscillator instead of its supply voltage, the proposed technique overcomes the limitations of conventional voltage regulator, achieves high supply-noise rejection performance and digital tuning of current-regulated...
