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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
A 10-bit single-channel SAR ADC is designed in a 130nm CMOS technology. An original DAC is proposed, merging a binary-weighted structure and a C/2C topology in order to reduce overall energy consumption. A built-in calibration circuit improves the conversion accuracy. The proposed SAR ADC samples at 6.66MHz, achieving a SNDR of 49.78 dB for a 1MHz input signal (ENOB of 8 bits). The simulated INL is...
A modified structure of operational transconductance amplifier (OTA) in CMOS 65-nm technology with signal-current enhancer and slew-rate (SR) helper is presented in this paper. The bias current is chosen to be lower than 0.1 μA to reduce the overdrive voltage requirement and thus make the amplifier survive under 0.7 V supply. An SR helper is also introduced to improve the transient performance. As...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency...
This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an...
A CMOS Super class-AB transconductor using Quasi Floating Gates (QFG) techniques to improve the speed and slew rate is presented. The QFG technique is applied to a static DC current source in the classic class-AB OTA, boosting the bias current for large input voltages. The new proposed OTA consumes the same static power as the traditional OTA, however the chip area is increased by 8.5% due to the...
We present a second generation current conveyor (CCII) based electronic interface for differential capacitive sensors. The sensor interface performs a capacitance-to-voltage conversion and has been designed in a discrete board as well as in an integrated version showing a linear input/output characteristic. Simulated and experimental results conducted on the discrete element board employing the low...
Using a new DC offset compensation method, a fully differential track and hold circuit is presented. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip...
The paper presents the description and analysis of a phenomenon, relating with successive approximation ADCs dynamic performance degradation due to the influence of impedance of the circuit that connects the reference source with the switched capacitors' common bus. The paper provides a detailed analysis of this phenomenon and demonstrates methods to mitigate its impact on the performance on switched-capacitor...
A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer. Proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order modulator in 90nm CMOS technology. Simulated SNDR of...
This paper presents the design and implementation of a CMOS transformer combiner that can be reconfigured to have similar efficiencies at widely separated frequency bands. Conventional transformer combiners employ a fixed tuning capacitance in the secondary network to optimize the efficiency for single frequency standard. In this work, we present a modified transformer combiner where digitally-switchable...
A compensation technique for recycling folded cascade (RFC) amplifier is presented. By applying the compensation technique, the proposed modified recycling folded cascade (MRFC) circuit achieves better slew rate and unity-gain frequency compared with RFC amplifier. The proposed circuit is designed using TSMC 0.18µm CMOS technology. The amplifier is verified with a 5.6pF output load under 1.8V power...
This paper presents a low power consumption LC-tank voltage controlled-oscillator (VCO). It is suitable for communication system of Integrated circuit. In this circuit, the operating frequency is generated by LC-tank. The circuit add a forward-bias circuit at the body to decrease the threshold voltage. Therefore, it can reduce the operation voltage and minimize the dc power consumption. This design...
This paper presents a novel area effective 2-tap speculative Decision Feedback Equalizer (DFE) with one switched-cap and one IIR summation for data self-correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. By using the switched-cap method, it is possible to get rid of duplicated...
In this paper, a low power three-stage CMOS amplifiers with 375x capacitive load (Ci) drivability will be presented. By employing the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively and the physical size of the compensation capacitors is reduced. A local Q-factor control (LQC) loop is introduced to optimize the Q-factor when loading capacitance Cl changes...
This paper presents a low-power fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator for battery-operated portable devices. A single stage high-gain telescopic cascode-compensated amplifier is used to attain good static performances, while thanks to a very simple dynamic bias circuit, transient performances are significantly enhanced with no quiescent current penalty. Results validate...
This paper presents a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers. The ADC is designed...
This paper presents a CMOS 1.8 V–0.18 μm quadrature sinusoidal oscillator designed for its application as the actuation system in portable frequency-domain sensing devices, such as impedance spectroscopy or resonant readout systems. It is based on an analog implementation, to preserve low-voltage low-power operation with a compact topology. The oscillation frequency can be digitally set by a novel...
This paper work is about a transimpedance amplifier which have very high gain and sensitivity designed using cadence CMOS 0.18 μm technology with supply voltage of 1.8 V dissipates power 43μW suitable for current sensing signals from a sensor, molecular and nanodevice system. The integrator based circuit followed by an ADC. Because of the ability to handle large standing currents, the circuit is competent...
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