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A modified structure of operational transconductance amplifier (OTA) in CMOS 65-nm technology with signal-current enhancer and slew-rate (SR) helper is presented in this paper. The bias current is chosen to be lower than 0.1 μA to reduce the overdrive voltage requirement and thus make the amplifier survive under 0.7 V supply. An SR helper is also introduced to improve the transient performance. As...
A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer. Proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order modulator in 90nm CMOS technology. Simulated SNDR of...
This paper presents a biopotential acquisition unit with an instrumentation amplifier and analog-to-information converter for wearable health monitoring applications. The instrumentation amplifier defines the quality of the acquired biopotential signals. At the heart of the system is an Analog to Information Converter (AIC) to enables the random under-sampling operation. AIC is used to digitize the...
A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above Vdd/2. As a result, during the comparison the second stage...
This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using TCC(Threshold Configuring Comparator) for the 5 MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um × 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling...
A low power switching method for SAR ADC is proposed in this paper. With this switching method the comparator first compares the sampled input voltage with Vref/2 to generate the MSB and determine whether to use Vref/2 or Vref as the comparator reference voltage in the following conversation steps, and the DAC with a split capacitor array uses Vref/2 as the reference voltage to generate the remaining...
This paper presents a low-power 11-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a self-dithering technique. The LSBs is employed as a dither to improve the resolution. Compared to converters that use the conventional dithering architecture, simulation results show that the proposed self-dithering technique improve the DNL performance with simplified...
This paper presents a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with 60.9 dB SNDR at 50MS/s while with 41.3uW power consumption. Several techniques were used to decrease the power consumption. First, Segmented architecture was used to decrease the total number of capacitance. Aligned switching with skip (ASS) method was used during copy MSB bits from coarse to...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
This paper presents a Verilog-A implementation of three different energy efficient architectures of Successive Approximation Register (SAR) analog-to-digital converter (ADC) namely SAR ADC with monotonic capacitor switching DAC, SAR ADC with split-monotonic capacitor switching DAC and SAR ADC with bypass window technique. These architectures were constructed for a resolution of 4 bits. Simulation...
In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal....
A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of...
The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited sampling rate which is due to its sequential operation. In flash-SAR architectures, this problem is mitigated by cascading flash and SAR ADCs which operate in two consecutive...
A hybrid DAC structure combined with conventional binary-weighted (CBW) capacitive array and pseudo C-2C capacitive array is proposed in the paper. Causes for nonlinearity of the structure are analyzed, including the effects of parasitics and the deviation of the capacitor adjustment parameter. Analysis of the power consumption and nonlinearity of the hybrid structure is also presented. This structure...
This paper presents a compensation method in which the phase margin and unity gain bandwidth of an Operational Transconductance Amplifier (OTA) is improved by addition a(n) active/passive resistive to the frequency compensation circuit. This improvement is achieved without changing the power consumption of the OTA. Based on the proposed strategy, three different compensation structures including RHC,...
This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier...
A design of opamp-sharing multiplying digital-to-analog converter (MDAC) used in the successive stages of an 80MS/s 14-bit pipelined analog-to-digital converter (ADC) with 1.8V supply voltage is presented in this paper. Opamp-sharing structure of the paper is proposed to achieve low-power operation, and SC-CMFB (switch capacitor-common mode feedback) circuit further reduces power consumption. The...
A 0.4V 6.5nW 10b 2.5kS/s SAR ADC is proposed for energy-limited applications such as wireless micro-sensor networks, biomedical, and energy harvesting systems. The ADC operates at extremely low supply voltage (0.4V) to reduce power consumption and to eliminate short-circuit current. The channel length of MOSFETs in digital block is optimized to minimize digital power consumption. Small unit capacitor...
This paper proposes a new method to raise the power of the Solid Oxide Fuel Cell (SOFC) stacks in a coal-fired SOFC-based power plant to solve the sulfur contamination problem of the SOFC stacks. Rather than rapidly raise the power demand from the DC link and therefore the SOFC stack in a single step, the method raises the power demand from the DC link gradually in multi-steps. As a result, a much...
This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted capacitors Digital-to-Analog Converter (DAC)...
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