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This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into partitions, and one number is replaced by two with zeros interlaced in every other partition. Products are computed with no carries between partitions, in the time required to multiply the short partitions and add the partial sums. Component adders and multipliers can be chosen to trade off area and speed....
Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing...
The gap between capabilities of CMOS technology scaling and requirements of future application workloads is increasing rapidly. There are several promising design approaches that jointly can reduce this gap significantly. Approximate computing is one of them and in recent years, has attracted the strongest attention of the scientific community. Approximate computing exploits inherent error-resilience...
As the days go by, the innovation in the technology is growing faster and smaller chips with more complexity in the design and implementation. Design of adders is prime importance in any given embedded application; hence the design of reliable and efficient adder on a VLSI based embedded application matters. In this paper we primarily deal with the construction of high speed adder circuits. Design...
In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve Low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The Circuit was implemented using Microwind tool in 90nm and 180nm technology. Performance metrics of power and speed are...
A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems. Today, efficient full adder circuit design is one of the main challenges for VLSI engineers. This paper proposes a novel 1-bit full adder circuit designed using N-MOS...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
Modern day technology has extended its reach below 20 nm. All kinds of effects are to be seen in MOS devices due to different leakage mechanisms at deep sub-micron levels. These lead to errors in the system. Error tolerance (ET), an emerging concept in the field of VLSI design and test: by easing the restriction on accuracy, can be used to have improvements in speed and power depending on the amount...
A processor executes a computing job in a certain number of clock cycles. The clock frequency determines the time that the job will take. Another parameter, cycle efficiency or cycles per joule, determines how much energy the job will consume. The execution time measures performance and, in combination with energy dissipation, influences power, thermal behavior, power supply noise and battery life...
Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry...
Multiplication is an important mathematical operation in many microprocessor architectures. And, multipliers have evolved dramaticlly after the late 1970s and have gone through tremendous changes with an aim of reducing the area and delay. This paper presents and an extension to Booth-3 multiplication architecture by implementing the partial product matrix in redundant form. It is anticipated that...
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
The fast performance of a carry-lookahead adder (CLA) comes from the ability to input a carry signal into each full adder block that depends on all preceding adder blocks. While the translation of this carry signal logic into CMOS transistors has a unique solution, this paper demonstrates that there are four different ways to connect the PMOS and NMOS transistors to Vdd, ground, and the output. Each...
The key parameters for the performance measure of any VLSI design are logic delay, power consumption and chip area. This paper describes the VLSI design of a 16 Bit ALU and design is optimized in terms of Speed, Power Consumption and Chip Area. Different logic families are used in the design for various logic modules. The choice of logic families for each module is determined by considering speed...
For many processing operation addition forms the basis, that is from counting to multiplication to filtering. As a result adder circuit are important therefore we have proposed design of quaternary adders such as quaternary ripple carry adder, quaternary carry look-ahead adder, quaternary carry select adder. The various quaternary adders shows power consumption of 64% less as compared to binary circuits...
Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS)...
In this paper, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace [5] and Dadda [6] in sub-threshold regime. In order to reduce the hardware which ultimately reduces an area and power, energy efficient basic modules AND gates, half adders, full adders and partial product generate units have been analyzed. At the last stage ripple carry...
In this work, an efficient hardware architecture of modulo 2n + 1 squarer is proposed and validated. The proposed modulo 2n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting...
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