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Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more likely to happen due to the continuous technology scaling down. Error Correction Codes (ECCs) are applied for recovering the stored information into its original state providing reliable computer systems. Several ECC are able to deal with MCUs, however, the higher the robustness of an ECC, more area, and energy...
Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation...
With the ever increasing process variability in recent technology nodes, path delay fault testing of digital integrated circuits has become a major challenge. A randomly chosen long path often has no robust test and many of the existing non-robust tests are likely invalidated by process variations. To generate path delay fault tests that are more tolerant towards process variations, the delay test...
Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional...
Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths Per Gate (KLPG) test approach, since path delay test has additional necessary assignments, compared to transition fault test. Some percentage of flip-flops is not scan, due to delay, area or power constraints. Their outputs are "uncontrollable"...
Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary...
With decreasing size of transistors, the impact oftransient faults as well as the local and global variability of transistors increases, affecting system functions and performances. Formal verification may be used to prove that a circuit isrobust against transient and parametric faults. However, a modelincluding timing information combined with extracted electricalparameters is typically too large...
Diagnosis of integrated circuits is an arduous process. Tools are needed which aid developers locating circuit's faulty parts faster. In this work path delay faults are considered. A simulation based diagnosis algorithm using diagnostic test patterns is introduced for locating the cause of the delay fault. Initial paths are segmented to improve the diagnosis accuracy. For each segment, additional...
Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor's characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. We present a conservative algorithm to decide if a transient fault leads to erroneous...
For high end design, delay test becomes increasingly important. The paper proposes a technique to synthesize fully delay testable circuit without any additional control input. Our proposal is based on covering each ROBDD node by Invert-And-Or elements. We have shown that the generated circuit is fully testable either by robust tests or by validatable non-robust tests.
Delay faults testing is more and more important due to huge number of gates and lines integrated on a chip. Path delay faults are tested via selected critical paths in a tested digital circuit. The critical paths can be specified e.g. By static timing analysis (STA), statistical static timing analysis (SSTA) and others. Signal delay propagation is also affected by many factors such as power supply...
A method is proposed for simulating of transition delay faults (TDF) at different fault propagation conditions. The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions like non-robust and functional sensitization. A new sensitization type, called nonrobust functional sensitization...
Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simulation result is expressed by a scalable data structure only proportional to the numbers of gates and...
The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are...
A new method is presented for simulating of transition delay faults (TDF). The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions. Three known fault classes of delay fault sensitization are considered: robust, non-robust and functional sensitization of delay faults. Additionally,...
Although path-delay faults (PDF) have been studied extensively during the last three decades, design of combinational circuits to achieve low-overhead robust PDF testability, still poses many challenges. In this paper, we revisit the problem of synthesizing a robust path-delay fault testable combinational circuit based on certain new functional properties. Given the boolean cubes of a function, we...
Delay testing is performed to guarantee that a manufactured chip is free of delay defects and meets its performance specification. However, only few delay faults are robustly testable. For robustly untestable faults, non-robust tests which are of lesser quality are typically generated. Due to significantly relaxed conditions, there is a large quality gap between non-robust and robust tests. This paper...
Recently several methods have been presented to measure the delay of a small set of path delay faults (PDFs), known as a basis set which is used to compute the delays of PDFs. All methods assume that the basis consists of strong robustly tested PDFs because their delays can be measured. This paper presents procedures to identify measurable PDFs whose delays otherwise could not be measured by traditional...
This paper concerns the problem of the delay-dependent robust stability for neutral singular systems with time-varying delays and nonlinear perturbations. Based on integral inequalities, some both discrete-delay-dependent and neutral-delay-dependent stability criteria are obtained and formulated in the form of linear matrix inequalities (LMIs). Neither model transformation nor bounding technique for...
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the post-production test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Today's ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate...
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