The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Formal verification has become very useful and popular in last decade in area of embedded systems design and in analysis of critical systems. It can reveal common errors like deadlocks, starvation, check system invariants, but also verify more complex properties defined by LTL formulas whose writing may be very error prone for non expert users. To reduce the time-to-market for embedded systems and...
High Efficiency Video Coding (HEVC) is the new video compression standard. A novel optimized architecture of Integer Motion Estimation (IME) for HEVC processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 43 fps (frames per second) with a frequency of 142 MHz and a latency of 402 clock cycles. The proposed design has been synthesized and simulated...
Random numbers are critical in every cryptographic fields. They can be used as cryptographic key, seed, nonce, initialization vector, etc. In this paper, new (pseudo) random number generator (PRNG or RNG) based on computer's source is proposed. The principle of method consist in collecting (nearly) random sources produced from computer and used it as seed for (pseudo) random number generation. Random...
Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular...
This paper presents a new low complexity architecture of least-mean-square (LMS) adaptive filter using distributed arithmetic (DA). The DA based LMS adaptive filter requires lookup tables (LUTs) for filtering and weight updating operation whose complexities grow exponential with filter order. In the proposed technique, the complexity of LUT for DA based LMS adaptive filter is reduced by two new serial...
A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous locally synchronous structure enables scalable...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
Ultrasound brain stimulation technology is a new method of brain stimulation which developed in recent years, with no damage, high spatial resolution, penetrating and so on, however, it is possible to lack of stimulate strength and not achieve the purpose of stimulation. For this, we design the driving circuit for ultrasonic brain stimulation based on FPGA in this paper, the system can drive multi-center...
The paper suggests very fast electronic solutions for priority buffers that take data from many potential sources, accumulate them in a register, and output the most priority item in run time in such a way that as soon as a new value arrives it is included in the set with all previously received and untreated items and properly handled. It is shown that such circuits are required for real time embedded...
In converters possessing multiple distributed controllers the synchronization of and the communication between the various controllers are important topics requiring careful consideration. The controllers should be able to transmit data and commands to each other so that different control modes can be selected, reference values updated, parameters shared and so forth. Synchronization is important...
In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation...
In today's high performance computing (HPC) environments, analyzing and predicting the performance of multiple-processor systems (clusters cores) on critical workloads remains a challenge. This is as a result of the key metrics that influences system's behavior. Busty arrivals in HPCs demand either a shared memory-parallel architecture or pipelined dataflow architecture. At present, a processor model...
This paper reviews the hardware requirements of generalised single photon ADC-less receiver circuits for visible light communications. A receiver based on parallel banks of pulse combiners and pipelined adders is shown to provide over a magnitude of circuit area reduction over the generalised structure.
We have proposed a method of designing embedded clock-cycle-sensitive Hardware Trojans (HTs) to manipulate finite state machine (FSM). By using pipeline to choose and customize critical path, the Trojans can facilitate a series of attack and need no redundant circuits. One cannot detect any malicious architecture through logic analysis because the proposed circuitry is the part of FSM. Furthermore,...
The Department of Homeland Security Cyber Security Division (CSD) chose Moving Target Defense as one of the fourteen primary Technical Topic Areas pertinent to securing federal networks and the larger Internet. Moving Target Defense over IPv6 (MT6D) employs an obscuration technique offering keyed access to hosts at a network level without altering existing network infrastructure. This is accomplished...
Although the Moore's law is slowing down in terms of technology node scaling, researchers are inventing new methods to keep the design productivity on the rising trend. As a consequence, the complexity of hardware designs will continue to grow, which results in further hardening of functional verification. Assertion based verification is well established and proven to be an effective RTL verification...
Large number multiplication has always been an essential operation in cryptographic algorithms. In this paper, we propose Broken-Karatsuba multiplication by applying the non-least-positive form to represent large numbers and dig the parallelism hidden in conventional Karatsuba multiplication. Further, we modify Montgomery modular multiplication algorithm with Broken-Karatsuba multiplication to make...
Clock glitches are useful in hardware security applications, where systems are tested for vulnerabilities emerging from fault attacks. Usually a precisely timed and controlled glitch signal is employed. However, this requires complex generators and deep knowledge about the system under attack. Therefore we present a novel approach on clock glitch fault attacks that replaces the single precise glitch...
The benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at runtime has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. This enables a result that is at least as accurate as the worst-case under...
Internet-of-things (IoT) paradigm exploits the Distributed Measurement System (DMS) to execute measurements. Each node of the DMS has computational and communicative capabilities, and can be equipped by sensors and measurement instruments. Therefore, it can be assumed as Smart Object (SO). The availability of mobile SO (MSO) (cars, smartphones, drones) is taken into consideration in the research to...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.