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DNA is considered as a good computing device because of the predictability of the double helical structure and the Watson-Crick binding thermodynamics associated with them. DNA circuits can be considered as a possible replacement of silicon transistor based circuits, in implantable medical devices, bio-nanorobots, SMART drugs etc. In this paper, we are proposing a novel five input majority logic gate...
A metallic-target reactive co-sputtering technology is used to fabricate zinc tin oxide (ZTO) thin-film transistors (TFTs). The effect of the O2/(Ar+O2) flow rate ratio on the performance of the resulting TFTs is investigated in detail. It is found that an O2/(Ar+O2) ratio of 11%–12% produces devices with the best performance, including a linear mobility of 8.6 cm2/Vs, subthreshold swing of 0.36 V/decade,...
Charge trapping properties of Al-ZrO2/Al2O3/ZrO2-SiO2-Si structures were investigated in attempt to elucidate the instability in their C-V hysteresis. The hysteresis in these structures is mainly due to subsequent trapping of electrons and holes injected from the Si substrate. However the competitive process of electron injection from the gate accompanied by the high leakage introduces instability...
Lateral GaN-on-Si HEMT technology enables integrated high-voltage half-bridges with gate drivers. However, the capacitive coupling through a common conductive substrate influences switching characteristics. The measured hard-switching turn-on time with floating substrate increased to over 16 ns as compared to conventional source-connected substrate (1 ns), switching 300 V/4A with GaN ICs comprising...
This work presents the operation of a PCB-embedded diode-clamped multilevel-converter integrated circuit (IC) fabricated in a lateral, high-voltage AlGaN/GaN-on-Si heterojunction technology. It is demonstrated, that PCB-embedding is an appropriate assembly technique for lateral power ICs with high-integration levels. By placing DC-link capacitors onto the IC-package, parasitc inductances in the power...
We present a TCAD process and analytical model based simulation analysis to investigate the effect of different stressors on nanowire FETs. We have utilized stress profiles extracted from TCAD process simulations and calculated mobility enhancement using the second-order piezoresistive model. Our analysis includes strained CESL and strained gate fill material for a gate-last process. Our process simulations...
Cathode related current collapse effect in GaN on Si SBDs (Schottky Barrier Diode) is investigated in this paper. Capacitance and current relaxation measurements on diodes and gated-VDP (Van Der Pauw) are associated with temperature dependent dynamic Ron transients analysis showing that the main part of the current collapse at the cathode comes from a combination of electron trapping in the passivation...
This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations...
This paper reports the epitaxial-Si growth and dopant diffusion characteristics during fabrication of a vertical thin poly-Si channel (VTPC) transfer gate (TG) structured pixel, which is a possible candidate for future three-dimensional (3D) CMOS image sensor (CIS). Due to the increasing demand for higher resolution sensor, major CIS companies have presented various innovative 3D pixel structures...
We present a study on multi-gate field-effect transistors that allow adjusting the potential landscape in semiconducting nanowires/tubes on the nanoscale. To this end, a damascenelike process is employed that allows fabricating a large number of gate structures that are contacted individually and exhibit lengths and inter-gate distances well below 10nm enabling to realize potential landscapes within...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
In this study, we present an integration routine for self-aligned ZnO nanoparticle-based thin-film transistors (TFTs) to be implemented on flexible electronics. As a proof of concept, first experiments were performed on a borosilicate glass, and subsequently the integration process was carried out on a polyethylene terephthalate (PET) substrate. The TFTs operate at low voltage (Von around 1 V) and...
Four-terminal (4T) polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) are fabricated at 300 °C by metal induced crystallization (MIC) using copper (Cu) on a glass substrate. We observed variations in the performance for top gate (TG) and bottom gate (BG) drives, although the gate stacks of both drives are same. This difference results from the quality of the poly-Ge/BG SiO2 interface,...
Demands for highly-fUnctional flexible nonvolatile memories are quite increasing to realize future flexible consumer electronic systems. We demonstrated and fabricated the ferroelectric-based memory thin-film transistors (Fe-MTFTs) on flexible poly(ethylene naphthalate) substrates using organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and oxide semiconductor...
This work demonstrates the trench P/N hybrid nanowires (NWs) channel junctionless thin film transistors (JL-TFT) with gate-all-around (GAA) structure. The GAA NWs hybrid JL-TFT exhibits the good electrical properties, including high ON/OFF current ratio (>106), subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). This trench hybrid P/N channel JL-TFT is simple to fabricate and highly favorable...
High performance and low power dissipation low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for integrating circuits on a glass substrats. To control the threshold voltage of LT poly-Si TFTs, we employed four-tsrminal self-aligned planar embedded metal double-gate LT poly-Si TFTs using high quality lateral large grained thin poly-Si films. Successful...
The amorphous Indium-Tin-Zinc Oxide (a-ITZO) was fabricated by using direct-current (DC) sputtering method. Electrical and chemical properties of a-ITZO thin film transistors (TFTs) fabricated on the polyimide (PI) substrate were investigated. The a-ITZO TFTs on the PI substrate exhibited the saturation field effect mobility of 8.93 cm2/Vs, subthreshold swing of 0.38 V/decade and high on/off current...
In this paper, twin gate rectangular recessed channel (TG-RRC) MOSFET with independent gate control is used to realize its application in digital electronics by using it as two input logic. The input logic is controlled by the independent gates which have different work functions (Φ1 for gate 1 and Φ2 gate 2) which are separated by oxide layer of 2 nm, thus controlling various electrical parameters...
In this study, we perform a top gate field effect transistor by using the integration of novel materials such as graphene as active channel and fluorinated graphene as dielectrics on flexible Polyethylene terephthalate (PET) substrate. These device shows high carrier mobility (∼969 cm2/v.s) at a drain bias of +0.5V. It shows good mechanical flexibility and electrical stability after bending measurement...
Butting and inserted pickup layout in MOSFETs leads to substrate resistance shunting effect and serious ESD robustness degradation. This work develops novel layout with external well/ diffusion resistance embedding between the substrate and the grounding terminal in the NMOS transistors. This layout method can greatly enhance ESD performance of the inserted pickup devices. The second breakdown current...
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