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To eliminate the worst-case timing margins, a 13-transistor holosymmetrical transition detector (HTD) is proposed for use in timing variation resilient systems. The HTD achieves low overhead and wide-voltage-range operation via monitoring the discharge at the floating node of two-stage CMOS inverters. Using local detection and global clock stalling, the system is stalled immediately for one cycle...
A technical implementation variant of a singlephase voltage source inverter control system with sinusoidal pulse-width modulation based on target-oriented control with control actions frequency reduction providing specified nonlinear dynamic properties of the sys-tem and reduced requirements for computing resources of the microcontroller. The control system under consideration provides sinusoidal...
A low power, high frequency positive edge D flip flop circuit is implemented. Its operating frequency is 5GHz with a supply voltage of 1.8 V produces a output at a positive edge triggered signal. It consists of 16 transistor which compel low power of 10.42 μW with a phase noise of −147dBc/Hz and output noise −154.77dB at offset frequency 1 MHz, Circuits is also tested at different corner frequency...
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
Post-Silicon validation is a major bottleneck in System-on-Chip (SoC) design methodology due to increasing design complexity and it is very difficult to detect all the design flaws at Pre-Silicon verification level. Timer module in an automotive microcontroller is used for many applications like power train, power steering, transmission control and chassis so validation of the timer module is very...
Clock glitches are useful in hardware security applications, where systems are tested for vulnerabilities emerging from fault attacks. Usually a precisely timed and controlled glitch signal is employed. However, this requires complex generators and deep knowledge about the system under attack. Therefore we present a novel approach on clock glitch fault attacks that replaces the single precise glitch...
Due to the technology scaling the critical charge stored in active nodes is reducing very drastically, so even very small amount of radiation charge could able to disturb the values stored in the active node. In this paper, we have proposed soft-error tolerant flip flop design. The proposed flip-flop utilizes a cross-coupled inverter on the critical path in the master-stage and generates the required...
The clock distribution network consists of the clocked tree and flip flops. In this paper we have designed sense amplifier energy recovery (SAER), static differential energy recovery (SDER), differential conditional capturing energy recovery (DCCER), signal conditional capturing energy recovery (SCCER) and self gated energy recovery (SGR) flip flops. Among these flip flops SGR flip flop is giving...
A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for...
We optimize and compare the performance of synchronous and asynchronous comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in...
In this paper a side-channel-attack resistant AES system with a variation-tolerant true Random Number Generator (tRNG) is implemented using IBM 0.13μm CMOS technology. As the random source for the AES, a meta-stability based tRNG takes advantage of an all-digital self-calibration method to compensate Process-Voltage-Temperature (PVT) variations, and thus guarantees output with extremely high randomness...
Secondary frequency control, i.e., the task of restoring the network frequency to its nominal value following a disturbance, is an important control objective in microgrids. In the present paper, we compare distributed secondary control strategies with regard to their behaviour under the explicit consideration of clock drifts. In particular we show that, if not considered in the tuning procedure,...
The application of consensus theory in the control of islanded microgrids (MG) is gaining increased attention because it facilitates the development of distributed control solutions. In particular, its application to active power sharing and frequency regulation has lead to satisfactory results. This paper analyses the effect that local clock drifts have in the parallel operation of voltage source...
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation...
In this paper, a voltage-scalable inverter-based operational amplifier suitable to be used in a reconfigurable ADC is optimized. A very low voltage sample-and-hold (SHA) circuit based on this opamp is presented to test the feasibility of a reconfigurable pipeline ADC. Simulations using STMicroelectronics 45-nm device models show that the opamp gain remains quite constant up to a supply voltage of...
Although CMOS technology scaling combined with efficient frequency and voltage scaling strategies offer femto Joule per logic operation, energy consumption remains orders of magnitude above the limit given by information theory. To alleviate this inherent energy dissipation, this paper introduces a new paradigm: the adiabatic capacitive logic. Based on adiabatic operation, the principle also relies...
Inversion over GF(2m) is crucial for cryptographic applications such as elliptic curve cryptography. The commonly used Itoh-Tsujii algorithm (ITA) computes the inversion by an entirely sequential process consisting of multiplications and squarings. In this paper, we first propose a modified ITA algorithm (MITA) for inversion with polynomial basis (PB). The MITA reduces the required clock cycles of...
We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two in standard 65nm CMOS technology. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the conventional approaches, this design uses a fully matched input stage, an unbalanced latch stage, and a two-clock operation scheme. A...
Scan based diagnosis plays a critical role in yield enhancement of sub-nanometer technology based chips. However, the scan chain itself can be subject to defects due to the large logic circuitry associated with it which constitute a significant fraction of total chip area. In some cases, it has been observed that scan chain failures may account for 30% to 50% of chip failures. Hence, scan chain testing...
With technology scaling, the vulnerability of combinational circuits is increased, so evaluating their reliability becomes an essential demand. In this paper a simple yet effective method is proposed to derive the reliability of a combinational circuit. The idea of this method is to prevent the complexity of the traditional methods that use multi-iteration statistical procedures. This goal is achieved...
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