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This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
This paper reviews the use of UHF double class-E (class-E2) topologies for dc/dc power conversion. After introducing this attractive resonant converter in the context of the time-reversal duality principle, two different lumped-element networks are described for appropriately terminating the drain of the switching devices. Recent implementation examples, taking advantage of GaN HEMT processes, are...
Z-source inverters (ZSIs), compared to the conventional two-stage architecture, embrace some interesting features, like the reduced size and complexity of the entire conversion system. Many research activities have been established to improve the performance of the so-called ZSI since it has been proposed in 2003, and several modifications have been introduced since then. These modifications include...
This paper proposes a Zero-Voltage Ride-Through (ZVRT) method and an LCL filter optimization design method to meet the Fault Ride Through (FRT) requirements for a singlephase grid-tied inverter with a minimized LCL filter. The inverter output current overshoots at a voltage sag when the small LCL filter is used. As a proposed method in this paper, the inverter output current overshoot is suppressed...
This paper presents a high performance 12 kW motor drive system for an aerospace application. In order to achieve higher power density and reliability, the system uses a PMSM motor, SiC MOSFET inverter, high performance PWM control, and liquid cooling with phase change material. A power density of 33 KW/KG was achieved for the power inverter and control electronics excluding the cooling loop, and...
This paper presents a selective harmonics reduction for a 3(n+1) shared switch inverter topology utilizing optimal arrangement of the n-modulated signal. Under different modulation indices and operating power frequencies the purpose of the proposed procedure is to select an optimal load connection and/or modulation offsetting based on the desired objective function. Three performance indices are studied...
High quality voltage and current are required when PV generator is connected to grid utility. To this, multilevel inverters are very desirable to be used as connection interface. To keep the cost of the whole system as low as possible, a cost-effective control device using STM32F4 discovery board is employed to control three-level inverter that can be used in grid-tied PV system. The paper develops...
In this paper, design considerations for transitioning from a Si-IGBT based inverter to a SiC-MOSFET based inverter are discussed. An existing Si-IGBT power structure is modified using a footprint compatible SiC-MOSFET module, with changes made to the power structure and gate drive for the high PWM switching frequency required for SiC devices. Design issues such as inductance minimization, EMC mitigation...
This work presents the operation of a PCB-embedded diode-clamped multilevel-converter integrated circuit (IC) fabricated in a lateral, high-voltage AlGaN/GaN-on-Si heterojunction technology. It is demonstrated, that PCB-embedding is an appropriate assembly technique for lateral power ICs with high-integration levels. By placing DC-link capacitors onto the IC-package, parasitc inductances in the power...
This paper shows the circuit level performance comparison of low-κ and high-κ spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-κ (HfO2, κ=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-κ (SiO2, κ=3.9) spacer J-FinFET....
Minnick counter is a special kind of electronic circuit that is employed to determine the number of ones in a binary input sequence. Here we have proposed a circuit which can determine the number of ones in a binary sequence. If we look close to the circuit then we may find that this circuit can also be used as a Full Adder circuit with a little alteration. The 3 bit Minnick Counter circuit can act...
This paper reports on the design and experimental verification of a 200 kVA traction inverter using three 900 V, 2.5 mΩ, SiC MOSFET-based half-bridge power modules comprising the power stage. Each dual power module contains four 900 V, 10 mΩ SiC MOSFETs per switch position and uses synchronous conduction to achieve high average and peak efficiencies over its entire operating region to meet the demands...
In this paper, key aspects of silicon-carbide (SiC)-based automotive traction drives are reviewed. Firstly, the required supporting factors to achieve optimal operating conditions and best performance are described. Major component sizing methodologies and constraints are included. Expectations on gate threshold voltage, trans-conductance, and transient oscillation are discussed. Tolerance against...
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the...
The quality of TRNG designs mainly depends on the grade of the noise source from which the entropy will be harvested to extract randomness. Especially for purely digital noise sources suitable for FPGA implementations the use of Ring Oscillators is suggested in many scientific publications. Standard Ring Oscillator based noise sources however have earned some criticism regarding the amount of entropy...
The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines...
Clock glitches are useful in hardware security applications, where systems are tested for vulnerabilities emerging from fault attacks. Usually a precisely timed and controlled glitch signal is employed. However, this requires complex generators and deep knowledge about the system under attack. Therefore we present a novel approach on clock glitch fault attacks that replaces the single precise glitch...
Advanced CMOS nodes target high-performance at lower supply voltage. High-mobility III-V channel materials have the potential to meet this target. Although III-V materials such as InGaAs are beneficial for nFET channels, SiGe (or Ge) provides better hole mobility and is more suited for pFET channels. Therefore, a InGaAs/SiGe hybrid CMOS technology is being pursued for scaled nodes. There are significant...
This paper introduces a control method for Reverse-Conducting (RC-)IGBTs which reduces the control dead time of RC-IGBT inverters. Switching measurements with 6.5 kV RC-IGBTs concerning the applicability of the introduced control method and the effect of a load current direction change during the desaturation pulse are presented.
Logic gates for ultra-low voltages suffer from speed and robustness degradations, which are highly associated with the process technology. In this work a methodology for the automated design-space exploration of standard logic gates for a 28 nm FD-SOI technology is shown. Comprehensive design space explorations of inverter and nand2 gates show the benefits of back-biasing at sub-threshold supply voltages...
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