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Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the...
A power-efficient analog beamforming embedded SAR ADC for ultrasound imaging systems is presented. It is constructed from multiple sub-beamforming SAR ADCs, which sequentially perform analog beamforming and analog-to-digital conversion for an assigned focal point on a scan-line. Power is saved because these operations are carried out in the charge domain without a summing op-amp. This is realized...
This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC...
Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular...
To eliminate the worst-case timing margins, a 13-transistor holosymmetrical transition detector (HTD) is proposed for use in timing variation resilient systems. The HTD achieves low overhead and wide-voltage-range operation via monitoring the discharge at the floating node of two-stage CMOS inverters. Using local detection and global clock stalling, the system is stalled immediately for one cycle...
A proposed phase-interpolator (PI) based hybrid digital pulse width modulator (DPWM) effectively resolves the trade-off between resolution and power consumption. Conventional DPWM delay-line-based architectures suffer from high power consumption limited delay time per delay-tap due to process technology, while the proposed solution replaces the delay line with a PI featuring sub-gate-delay resolution...
This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers...
This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency...
In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro,...
Ensuring accurate testing of a UHF electronic package is the main requirement for a testing system. There are two problems: metrological certification as generator devices generating test pulses of desired amplitude and at a desired moment of time and the problem of measuring amplitude and time parameters of signals at the outputs of an electronic package. This paper observes the methods of measurement...
An energy-efficient self-charged crystal oscillator (SCXO) employing a quadrature-phase shifter is proposed to provide wide-range pulse injection timing for power consumption reduction. The passive resistors of quadrature-phase shifter can be shared by the startup circuit to save area consumption. The double-edge extractor and the low-power comparator are added to reduce the power consumption. The...
This paper presents an integrated Analog Delay Line (ADL) for analog RF signal processing. The design is inspired by a Bucket Brigade Device (BBD) structure. It transfers charges from a sampled input signal stage after stage. It belongs to the Charge Coupled Devices (CCD). This ADL is fully differential with Common Mode (CM) control. The 28nm Fully Depleted Silicon on Insulator (FDSOI) Technology...
Integrated digital circuits are frequency capped by its heavily constrained paths between flip-flop stages. These so-called critical paths are highly susceptible to delay fluctuations leading designers to use guard-banding in order to avoid timing violations. Several effects can cause these variations, whereas aging is of rising importance. Many works have addressed this issue through monitoring of...
A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to...
This paper discusses the time synchronization issue in wireless sensor networks. An event-triggered average consensus time synchronization algorithm is proposed. This algorithm uses the average time message from one node's one-hop neighbors to update the clock parameters of the node. And it achieved acceptable synchronization accuracy. We also proposed an event-trigger mechanism to reduce the communication...
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
In DVE systems, maintaining the consistency of event execution time is the core element to provide a unified view for all nodes in the system. However, owing to the fluctuation of message transmission delay within the network, some events cannot be executed at the expected time set by the sending node., It will seriously impact the interactive experience of the user in the virtual environment, especially...
The paper suggests very fast electronic solutions for priority buffers that take data from many potential sources, accumulate them in a register, and output the most priority item in run time in such a way that as soon as a new value arrives it is included in the set with all previously received and untreated items and properly handled. It is shown that such circuits are required for real time embedded...
Multi-power-mode designs have been widely used in industry for reducing the power consumption. However, in an ultra-low voltage design, a huge clock skew may occur among different power modes. The previous work has proposed a two-stage approach to eliminate this huge clock skew, but they do not consider the skew caused by the on-chip-variation (OCV) effects. In this paper, we propose an approach to...
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