The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A power-efficient analog beamforming embedded SAR ADC for ultrasound imaging systems is presented. It is constructed from multiple sub-beamforming SAR ADCs, which sequentially perform analog beamforming and analog-to-digital conversion for an assigned focal point on a scan-line. Power is saved because these operations are carried out in the charge domain without a summing op-amp. This is realized...
The era of internet of things (IoT) envisions a world where electronics is integrated with our environment. This can be achieved with ubiquitous low power sensing devices. It is challenging to achieve low power computing in the IoT paradigm since most applications are data-centric. However, typical applications have low duty cycle processing where idle times can be exploited for energy savings. This...
This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator...
Lightweight cryptography (LWC) provides cryptographic solutions for resource-constrained devices such as RFID tags, industrial controllers, sensor nodes, and smart cards. LWC based devices have stringent constraints on power consumption and are vulnerable to side-channel attacks such as Differential Power Analysis (DPA). The existing CMOS-based countermeasures for DPA are not suitable for circuits...
A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
This paper presents a 15-bit ΔΣ ADC with 10kHz-BW which can handle 30V CM voltages with high AC CMRR (in excess of 115dB at 10kHz) while operating from a 1.8 V supply. An HV capacitively-coupled chopper at its input enables the accurate sampling of input signals beyond the supply rails. Chopping is used to mitigate the ADC's offset and to enhance its CMRR, especially at high frequencies.
An incremental delta-sigma modulator with a self-making capacitor having a high voltage operating ability for a 12-cell battery pack is proposed in this paper. The measured voltage range for each battery is from 0 to 5 V, and the maximum input voltage reaches to 60 V. The self-making capacitor adopting a metal over poly silicon with a relatively thin layer of oxide between the two plates is generated...
This paper presents an integrated Analog Delay Line (ADL) for analog RF signal processing. The design is inspired by a Bucket Brigade Device (BBD) structure. It transfers charges from a sampled input signal stage after stage. It belongs to the Charge Coupled Devices (CCD). This ADL is fully differential with Common Mode (CM) control. The 28nm Fully Depleted Silicon on Insulator (FDSOI) Technology...
In this paper, a novel nonlinear impulse sampler is presented. The architecture uses an ultrafast transmissionline based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 ps. The chip is fabricated in IBM 9HP BiCMOS process technology and occupies an area of 1.02 mm2. The power consumption...
The power efficiency and performance of fully integrated charge pumps are highly dependent on the types of capacitors used in the pumping stages. A sample but not so well-known circuit technique that can minimize power losses is charge recycling applied to the parasitic capacitors always allocated with the useful capacitors at the core of every pumping stage. This paper discusses the possibility of...
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
Correlated double sampling(CDS) operation is generally used in CMOS imaging systems, implemented by switched capacitor(SC) circuits, to get rid of reset noise and decrease flicker noise. This paper presents an optimization method for the noise performance of a CDS circuit, the advantage of which is its ability of canceling the offset of the OP involved. The structure of the CDS circuit is analyzed...
A 27.6 MHz 297 μW relaxation oscillator is presented in this paper by using an 180-nm CMOS technology. The proposed oscillator employs an adjustable temperature compensation feedforward scheme, in which the charging current can be set steady by a four-bit digital trimming signal. We have demonstrated a frequency variation lower than 33.5 ppm/°C which could be close to 0 ppm/°C in theory if the precision...
We present a circuit for strain and vibration sensing from piezoelectric film elements (PVDF). The target application is the monitoring of low-frequency vibration in a biomedical wearable device. Since standard PVDF sensors produce an open-circuit voltage that is too large for direct amplification on an integrated circuit, the circuit performs input signal folding as well as output voltage attenuation...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.