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This paper makes a comparison between various quasi-delay-insensitive (QDI) asynchronous ripple carry adders (RCAs) realized using a delay-insensitive dual-rail code which correspond to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The QDI RCAs considered are 32-bits in size and correspond to a variety of timing regimes viz. strong-indication, weak-indication, early output,...
With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to...
The Gabor filter has gained an important agreement in multimedia processing and visual search applications for its good spatial frequency and position selectivity, notwithstanding its heavy computational load. For these reasons, Gabor filters find useful applications in the processing of medical images, aiming to enhance the original image and to overcome issues related to noise and artifacts. With...
Arithmetic circuits like adder, multiplexer etc. arethe most important circuits in digital signal processing andmany more applications. Full adder circuit is the basic cell ofarithmetic circuits. Many applications require circuits of highthroughput, small area and consume ultra-low power. In thisregards, this paper brings forward a new full adder circuitthat uses 10-Transistors and improved version...
Approximate computing techniques have paved new paths to get substantial improvement in speed and power efficiency by making a trade-off with the accuracy of computations in inherently error tolerant applications, like from image and video processing domains. The accuracy requirements of various applications can differ from each other. Even within a same application different computationscan have...
This paper proposes a highly defect tolerant Parallel Prefix Adder (PPA) design. Motivated by the inherent defect tolerance capability displayed in a Kogge Stone Adder (KSA), this paper identifies the key elements that can be applied to make the general PPA's defect tolerant: 1) the Generate and Propagate computing hardware is divided into disjoint groups, such that defects in one group will not “contaminate”...
The Parallel Self Timed adder (PASTA) is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits and do not need any of the carry chain propagation. The main objective of this paper is to reduce the power consumption and also to increase the performance. The existing design attains good performance over random operand conditions without any...
Digital computations and calculations is involved in every embedded and processing device, these devices has arithmetic logic unit or a special block to perform a desired operation, Addition can be one such operation, adders are most important and fundamental block used for Addition, Subtraction, Multiplication, Division, Address generation and so on, design and selection of adders for a embedded...
Modulo (231-1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (231-1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes...
While sub/near-threshold design offers the minimal power and energy consumption, such approach strongly deteriorates circuit performances and robustness against PVT (process/voltage/temperature) variations, leading to gigantic speed penalties and large silicon areas. Inexact and approximate circuit design can address these issues by trading calculation accuracy for better silicon area, circuit speed...
Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique...
In this paper, a high speed 256-bit carry look ahead adder has been designed using 22nm strained silicon technology. The proposed adder combines the advantage of both the static and dynamic designs, which exhibits lower leakage, higher noise immunity and high speed. The speed performance of the proposed 256-bit adder is significantly improved by computing the even and the odd carries separately by...
This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
Parallel prefix circuits have drawn high interests because of its importance in many applications such as fast adders. Most proposed parallel prefix circuits assume fixed width. The input size could be of the same width as the circuit or different than the width of the circuit. In this paper, we propose a class of reconfigurable parallel prefix (RPP) circuits, Ř-circuits, that support...
Utilizing Binary Signed-Digit (BSD) number representation in RNS arithmetic is called BSD-RNS. Up to the present, 2's complement BSD-RNS has been proposed. In this work, we utilize 1-out-of-3 encoding to represent residues in BSD-RNS. This paper proposes efficient modular multipliers for the moduli set {2n-1, 2n, 2n+1} based on 1-out-of-3 BSD number system. Compared to efficient 2's complement BSD-RNS...
In [1,2], K.-J. Cho et al. proposed a 7-bit unsigned high performance parallel squarer design, using pre-calculated sums of partial products. This paper presents two improved implementations of this technique. The first implementation is based upon optimized interconnections between generation and reduction stages of the squarer. The second implementation is built using a hierarchical carry look-ahead...
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