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Due to the scaling of devices in nanometer regime speed and power related issues rises in digital circuits. Carbon nanotube field effect transistor (CNTFET) has been used in the present work as a low power circuit element. The major advantage of CNTFET is low power and energy consumption as compared to the conventional CMOS. This paper proposes the basic implementation of CNTFET inverter, MUX and...
Microgrids gathered a lot of attention in the last decade and are believed to be the future power systems. The renewable energy sources can be easily integrated into the Microgrid. Renewable energy sources such as PV, wind and fuel cells are usually connected through voltage-source inverters in the Microgrid. In order to share the same loads, these inverters are connected in parallel and to achieve...
Magnetic logic is considered as one of the alternate technologies to the existing CMOS engineering in designing digital logic circuits. In magnetic logic, the spin directions are considered as logic levels instead of electric charge used in CMOS modules. If magnetic dots are suitably arranged, antiferromagnetic and ferromagnetic coupling can be utilized to represent a digital circuit. In this paper,...
Adiabatic circuits have been one of the preferred designs for reducing overall power dissipation in a circuit. By adiabatic technique, power dissipation in PMOS network can be reduced to optimal rates and some of energy stored at load capacitance can be recycled instead of losing it in the form of heat. Here in the given paper, the efficient charge recovery logic (ECRL) has been used to design one...
This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power supplies and control voltages. The simulation results shows that the circuit has higher tuning range and low power consumption suitable for various application domains...
The Delay and Speed plays a complementary role in ICs, as the delay decreases the speed increases and vice-versa. The scaling of MOSFETs has resulted in reduction in size of ICs. As we scale down to nanometer regime, the Short Channel Effects (SCEs) of MOSFET affects the system performance and reliability. Here in this paper we discuss on FinFET, which is an alternate MOSFET, through which the SCEs...
This paper details preliminary results for a novel statistical analysis, using the delay of an inverter (the basic element of SRAM cells) as an example. The results obtained are statistically meaningful, and should allow for more accurate, faster, and better yield estimates.
Vertical transistors are one of the promising alternatives to standard lateral device structures in future technologies due to benefits in terms of reduced footprint and feasibility of fabrication of hetero junction structures. While such device-level benefits have been widely explored, the circuit and layout-level implications of vertical transistors require further analysis. In this work, we carry...
This paper presents the design and performance analysis of a ring oscillator using CMOS 90nm technology. A ring oscillator contains odd number of cascaded inverter in which output is oscillating between high and low level. Inverter with minimum delay is best choice for frequency generation. Delay of inverter can reduce by adding secondary inputs and switching these earlier than the primary inputs...
To analysis leakage current and delay for Double Gate MOSFET with Single gate MOSFET at 45nm in CMOS Technology by using the Cadence Virtuoso simulation tool. When compared to single gate MOSFET, the leakage current and delay are observed to be reduced in double gate MOSFET. The drive current remains the same for both single and double gate MOSFET based on Vgs but the short channel characteristics...
Carbon Nano-Tube Field Effect Transistors (CNFETs) are considered to be a promising candidate beyond the conventional CMOSFET. It is due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs determine current driving capability,...
This paper present an analytical model of delay for subthreshold voltage to time converters (VTCs). The model characterizes an equation between the input voltage and output delay. Delay prediction model can be used to compute delay and understand characteristic of VTC in subthreshold region. Simulations are done in 0.18um CMOS technology and results ensure the accuracy of the model.
Carry select adder is fastest adder but it required more area and power. The modern VLSI design systems are small in size and less power consumption so the modification is need in the carry select adder to achieve the reduced area and less power consumption. Two proposed works are introduced in thispaper. First method include the reduction of area and power in Carry select adder by modifying the EX-OR...
High speed, small-size and low-power consuming devices and systems is the considerable solution for next generation technological solution. The search for new principle of operation of the small-size, high speed and low-power device is becoming more and more important. Hear we studied two dimensional SOI and SON Inverter in nano scale, as well as Power dissipation and Delay is being calculated. We...
A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability...
The CMOS technology attained remarkable progress and advances. This progress has been achieved by downsizing of the MOSFETs. The dimensions of the MOSFETs were scaled by factor s, which has historically found to be 0.7. In VLSI technology, power and delay analysis have become crucial design concern. This paper emphasizes the comparative study of delay, average power and leakage power of CMOS inverter...
This paper focuses on minimizing the Power consumption during Write and Standby operations and delay during Write in a 6T-SRAM cell by using a new Proposed architectural design in 32 nm technology and comparing the results with the architectural designs being used nowadays. As microprocessors and other electronics applications get faster and faster, the need for large quantities of data at very high...
In this paper a new current comparator is proposed which offers high speed and high resolution while maintaining low power dissipation. The design improves upon previous Traff current comparator by modifying the given gain stage which leads to up to 83% improvement in delay. Simulation results performed on SPICE using TSMC 0.18µm CMOS technology demonstrate that proposed current comparator has a resolution...
Delay blocks are an important building block of signal processing circuits. To a great extent, performance of such circuits depend on the efficient design of delay blocks. In this work, a new scheme for designing a high delay chain is presented precisely for low frequency applications. The proposed design is based on the fact that propagation delay of a CMOS inverter increases with scaling down of...
A TSV in a 3D IC could suffer from two major types of parametric faults — a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize...
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