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Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the...
Cooperative intelligent transportation systems have become an active topic with the introduction of smart communications between vehicles, increasing driver safety, traffic efficiency and ultimately paving way for autonomous vehicles. These vehicular communications have stringent transmission requirements. Among various proposed communication protocols, use of heterogeneous networks, combining long...
Compressors are commonly utilized in multipliers for reducing partial products in a parallel manner. In this paper 7–3, 7–4, 8–3, 8–4, 9–3, and 9–4 compressors designed with adder circuits or multiplexer circuits were implemented in Altera EP2C70F896 FPGA and their performance compared in terms of number of logic gates used, cell area and power delay product (PDP) for an optimum recommendation for...
Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration,...
Adders are the main components in digital designs not only in additions but also in filter designing, multiplexing, and division. The circuit performance depends on the design of base adder. The demand of high-performance VLSI (very large scale integration) systems is increasingly rapidly for used in small and portable devices. The speed of operation is depends on the delay of the basic adder and...
Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. Furthermore, due to their inherent robustness, such circuits are also promising for deep voltage scaling applications, where delays are orders of magnitude larger. However, QDI design...
A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to...
This paper proposes a Zero-Voltage Ride-Through (ZVRT) method and an LCL filter optimization design method to meet the Fault Ride Through (FRT) requirements for a singlephase grid-tied inverter with a minimized LCL filter. The inverter output current overshoots at a voltage sag when the small LCL filter is used. As a proposed method in this paper, the inverter output current overshoot is suppressed...
Recently, with research and development of SiC power devices, 1.2 kV SiC MOSFETs have become commercially available. The parasitic parameters, such as output capacitance, in each power device are not identical, because they depend on the device structure and material properties. Therefore, voltage sharing of turn-off operations under series-connection conditions of the power devices may be affected...
Owing to the high current density but smaller die area of SiC components, high current SiC power modules typically feature a large number of parallel connected dies. Due to the faster electrical dynamics of these power modules, and the inherent mismatch of properties between the dies, certain dies can be poorly utilized — requiring either more dies to achieve a given current rating or a de-rating...
A novel non-volatile 1-bit binary comparator based on pure memristors and an 8-bit comparator based on 1T1M (1 transistor per memristor) crossbar array are proposed in this paper. The proposed comparator is sneak-path free and has short delays. It can be extended to an arbitrary N-bit comparator with 7N memristors and 7N transistors. The worst case input-to-output delay is 4.8ns. A 64-bit comparator...
Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate...
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
The insulation capability is a key indicator for designing a vacuum interrupter. A vacuum discharging process, especially the initial stage of it, is correlated to the capability. However, the effect of anode is still uncertain in a vacuum discharge process. The objective of this paper is to experimentally investigate the effect of anode on the initial stage of a vacuum discharge. A ICCD camera was...
This paper shows the circuit level performance comparison of low-κ and high-κ spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-κ (HfO2, κ=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-κ (SiO2, κ=3.9) spacer J-FinFET....
Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
This paper presents an addition and multiplication computation cell using pulse train time amplifier (TA) and time register (TR), which could be easily extend to large-scale computation. The proposed pulse train TA exploits a delay cell ring to realize large input range. In TR a gated delay line with MOS capacitor is adopted to achieve both large number computation and high resolution. Finally, a...
Reversible logic gate has gained importance in recent times due to its low power dissipation and less information loss. QCA on the other hand has low power consumption and has applications in reversible logic. In this paper, a 4×2 priority encoder is proposed which is based on reversible logic implemented in QCA. Firstly, this paper discusses about QCA layout design of Fredkin gate and Universal Reversible...
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