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The feasibility of using commercial CMOS processes for implementing scalable cryogenic control electronics for universal quantum computers is investigated. Using a systems engineering approach, we break the system down into sub-systems and model the individual components down to transistor level. First results for area demand and power consumption indicate that even with a standard CMOS process, it...
This paper demonstrates that our very thin film STO capacitor can be located under re-distribution layer (RDL) of WLP/FO-WLP package and is effective for reduction of the power supply noise of LSIs. Their Shmoo plots show improvement of operable frequency and power supply voltage reduction, as results of the improved power integrity realized by our Sub-RDL STO thin film capacitors.
A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the...
This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area...
A modified structure of operational transconductance amplifier (OTA) in CMOS 65-nm technology with signal-current enhancer and slew-rate (SR) helper is presented in this paper. The bias current is chosen to be lower than 0.1 μA to reduce the overdrive voltage requirement and thus make the amplifier survive under 0.7 V supply. An SR helper is also introduced to improve the transient performance. As...
This paper shows the design of a self-powered wireless digital sun sensor (including magnetometer). The information of satellite attitude and magnetic field intensity can be transferred to the attitude determination and control system (ADCS) through Bluetooth. Four solar cells in parallel connection and a super capacitor make sure that the sun sensor can work both in sunshine and shadow areas. The...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
An ultra-low power regulated charge pump system based on charge recycling between a tank capacitor and the charge pump output load capacitor is presented. The proposed circuit is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. Simulation results show a maximum current reduction of about 38% compared to a conventional regulated charge pump system. Rise time until...
A CMOS Super class-AB transconductor using Quasi Floating Gates (QFG) techniques to improve the speed and slew rate is presented. The QFG technique is applied to a static DC current source in the classic class-AB OTA, boosting the bias current for large input voltages. The new proposed OTA consumes the same static power as the traditional OTA, however the chip area is increased by 8.5% due to the...
This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900...
A low-voltage, ultra-low power sensor interface for electromyogram (EMG) signal acquisition is presented. The sensor interface consists of an amplifier and a SAR ADC that work from a 0.3V supply. The low-voltage amplifier topology provides a noise level of 26μVrms, 40dB gain and a state-of the art power efficiency factor (PEF) of 2.2 from a 20–425Hz bandwidth. Low-voltage supply improves the power...
This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V,...
This paper presents a low power programmable 12-bit Two Step successive approximation register (SAR) — Flash analog-to-digital converter architecture for communication and bio-potential signal processing applications. The proposed ADC consists of two identical 6-bit SAR-Flash analog-to-digital converter (ADC) stages combined with a pipelined inter-stage gain amplifier to improve performance, reduce...
This paper presents a constant bandwidth switched-capacitor programmable-gain amplifier (SC-PGA). By using an adaptive Miller compensation technique for the SC-PGA, our SC-PGA achieves low power consumption and high linearity at various gain conditions. The post-layout simulation results with 0.18 μm CMOS process show that power efficiency is tripled over the SC-PGA without the adaptive Miller compensation...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
The ever-increasing need for higher number of neural recording channels along with the stringent power and area requirements of a brain-implantable device, demand for ultra-compact and scalable channel architectures. In this paper, we will first briefly discuss the fundamental scaling issues of conventional AC- and DC-coupled neural front-ends. Next, we will analytically examine the feasibility of...
In this paper, the minimum total required transconductance for the different architectures of the pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. It is shown that the Algorithmic-Pipelined ADC requires a simpler Sub-ADC and shows lower sensitivity to the Multiplying...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further...
In this paper, a novel ultra-low power, programmable gain instrumentation amplifier (PG-IA) for biomedical signal processing applications is presented. The fully differential PG-IA employs a new rail-to-rail current mirror input pair with three stage indirect compensation (RR-CMI) amplifier. The proposed design improves the dc offset by implementing a fully symmetrical structure and is further reduced...
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