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This paper evaluates the benefits of using a high-level synthesis (HLS) tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems. The investigated workflow generates a synthesizable hardware description from a system level C-code along with a set of directives that specify performance criteria such as area utilization and timing closure requirements...
In this paper we focus on the issues of hardware implementation of genetic algorithms (GA) in hardware. In their classic implementation, the genetic algorithms search for a global minimum or maximum of a multidimensional function called the fitness function. If the problem, i.e. the fitness function, is too complex for a brute force search, we can look for a solution based on GA. In this situation...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
Post Silicon Validation is critical step in order to deliver quality microcontroller chips to customers but is increasingly becoming complex and time consuming process as the design size is increasing. Due to increased number & diversity of design intellectual property, microcontroller post silicon validation has moved towards customized validation concept and hardware setup for individual design...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom...
This paper presents a Field Programmable Gate Array (FPGA) based implementation of the Fourier Segmentation process that is used in the Empirical Wavelet Transform. The Empirical Wavelet Transform is a method to determine the modes of a given signal by building wavelets that are adapted to the processed signal. Such wavelets are constructed by determining the location of the information in the spectrum...
In fields like embedded vision, where algorithms are computationally expensive, hardware accelerators play a major role in high throughput applications. These accelerators could be implemented as hardwired IP cores or Application Specific Instruction-set Processors (ASIPs). While hardwired solutions often provide the best possible performance, they are less flexible then ASIP implementation. In this...
Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly...
Sophisticated embedded systems are increasingly used in defence, aerospace and avionic industries. They are responsible for control, collision avoidance, pilot assistance, target tracking, navigation and communications, amongst other functions. In this industrial field, High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons...
Due to the proliferation of reprogrammable hardware, core designs built from modules drawn from a variety of sources execute with direct access to critical system resources. Expressing guarantees that such modules satisfy, in particular the dynamic conditions under which they release information about their unbounded streams of inputs, and automatically proving that they satisfy such guarantees, is...
In this paper, we propose a novel high-speed and SPA-resistant architecture for elliptic curve cryptography (ECC) point multiplication. A new Karatsuba-Ofman based pipelined multiplier is proposed to lower the latency, and an improved comb point multiplication method is employed to reduce the clock cycles and to resist simple power analysis (SPA). The proposed ECC architecture has been implemented...
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
Field Programmable Gate Arrays (FPGAs) excel at the implementation of local operators in terms of throughput per energy since the off-chip communication can be reduced with an application-specific on-chip memory configuration. Furthermore, data-level parallelism can efficiently be exploited through socalled loop coarsening, which processes multiple horizontal pixels simultaneously. Moreover, existing...
This paper presents a new tool flow to realize algorithms in floating-point precision on FPGAs. A customizable multicore soft GPU architecture is used on the hardware side. Two solutions to perform floating-point arithmetic in IEEE-754 single precision are investigated: using standard function calls to GPU-friendly software implementations, or by hardware upgrades to the Processing Elements (PEs)...
The Intrusion Detection Systems (IDS) is becoming important and quite timing/space consuming due to the increasing volume of explosive data flood. During the past decades, there have been plenty of studies proposing software mechanisms to exploit the temporal locality in the IDS systems. However, it requires considerable memory blocks to store the redundancy table, therefore, the performance as well...
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced:...
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