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Silicon Carbide (SiC) power devices with super-cascode structure provide a cost-effective solution for high performance medium voltage power switches. However, these SiC super-cascode devices are still in the early development stage, and limited information on the device characteristics is available. This paper presents the characterization and evaluation of a 4.5 kV, 40 A SiC super-cascode device...
In this work, we demonstrate a way to modulate threshold voltage of InGaAs Fin-structured High-electron-mobility transistors (Fin-HEMTs) by narrowing fin width of the devices. Normally-off InGaAs FinHEMT has been successfully achieved when fin width of devices is smaller than around 180 nm. Also, we introduce a theory to explain side wall gates control of FinHEMTs to modulate threshold voltage.
Silicon co-implantation into PMOS FinFET fabrication is presented. The co-implantation method is applied at the source and drain to enhance transportation properties of the devices. The device is fabricated using an industry oriented tool, Sentaurus TCAD. Performance assessment is performed on two electrical parameters, which are threshold voltage and driving current. The simulation results show that...
A 3-Dimensional (3D) strained Silicon Nanowire MOSFET simulation and inversion charge model are presented. The simulation studies are conducted based on electrical parameters of nanowires such as current and threshold voltage using a ATLAS TCAD simulator. The inversion charge model with Germanium fraction is formulated using a unified charge model. These characterization studies are performed to investigate...
Aging and soft errors have become the two most critical reliability issues for nano-scale CMOS circuit. First, in this paper, the aging effect due to bias temperature instability (BTI) is analyzed on different logic gate using 45nm Technology, and simulated the critical charge and delay which can influence soft error rate (SER) result. Second, a method of SER calculation considering BTI effect is...
With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to...
Germanium is a promising material for future VLSI devices, due to its high hole mobility. However, due to the low bandgap of 0.66 eV Ge based devices typically suffer from high reverse junction leakage und therefore high static power dissipation. In this paper, we apply a nanowire structure with multiple independent gates to suppress the leakage in off-direction to achieve off-current levels below...
Deeply understanding how FinFET transistors behave causes a lot of interest and attentions. Mostly, the current, IDS, flows through the strongly-inversed layer about hundreds of angstroms in the channel of an enhancement-mode MOSFET device as a bias exceeding the threshold voltage is applied to Gate. As for FinFET devices, there are two features that are intriguing. For one thing, the leakage current...
We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in transistor mode, with back-gate biasing. These devices featured P-type field-effect characteristics suitable for future use as sensors. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as effective low field...
The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
This paper introduces a novel reduced short channel effects in nanoscale SOI MOSFETs by C-shape silicon window inside the channel, source and buried oxide. This work investigates the main characterizations such as maximum lattice temperature, subthreshold swing, DIBL, threshold voltage roll-off which all of them show the superiority of the proposed structure compared to the conventional SOI MOSFET...
We propose an arrayed test structure to assess the damages of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed under back-side LSI processes, such as by Focused Ion Beam (FIB). Back-side process with FIB is becoming essential to analyze and repair modern LSI chips, to avoid processing through many metal layers with dense wiring and dummy patterns. To access transistors from back-side,...
Process variation is a conspicuous predicament for sub-micron VLSI circuits. In this paper, we illustrate “choke points” as a vital consequence of process variation in the Near Threshold Computing (NTC) domain. Choke points are process variation affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors...
In general, an insulating film of SiC MOSFET is SiO2 formed by thermal oxidation of SiC. This SiO2 film has many defect structures which induce much larger threshold voltage shift. In this paper, we investigated the defect formation of an oxygen vacancy in SiO2 by SiC thermal oxidation, using the first-principles calculations, and we found that the oxygen vacancy defect can be generated in the amorphous...
Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (VDD) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked...
This paper gives a proper characterization of n-channel UTBOX nMOSFETs in linear operation in term of static performances and low frequency noise behavior. At first, the main electrical parameters are extracted, in particular, the threshold voltage, the mobility and the access resistances. Then, the approach of low frequency noise study is presented as a non-destructive diagnostic tool to identify...
Threshold voltage (VTH) needs to be well controlled to determine the switching point of the transistors. However VTH variation was observed on high voltage transistor during development phase. Investigations show that the VTH variation was caused by phosphorus contamination from wafer backside. Various wet chemical cleaning methods were evaluated to understand the effectiveness for the phosphorus...
Advances in technology has allowed us to demand for high speed and low power devices in modern chips. These transistors are scaled down and examined with multi-gate architecture in order to improve electrostatic control over the channel and reduce power consumption. A novel dual-gate gate-all-around (GAA) junctionless nanowire transistor (JNT) is addressed in this work. Using TCAD device modeling,...
Quantum definition based threshold voltage calculation of Gate-All-Around Junction Less Nanowire Transistor has been presented in this work. Employment of this approach has not yet been achieved on GAA-JLNT even though similar determination was previously established for TG FinFETs and GAA-MOSFETs in recent literature. The self-consistent solver, which takes wave function penetration and other quantum...
Advances in short channel transistor technology has allowed the emergence of these devices in modern chips. These transistors experience many different types of Short Channel Effects (SCE) that are addressed in this work. Using TCAD simulations, we report a new and effective technique to reduce SCE in a novel dual-gate silicon nanowire Gate-All-Around (GAA) junctionless transistor. A channel length...
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