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This paper presents the system that allows SEFI modelling by means of injecting upsets in different microcontroller memory blocks, carrying out its functional control and detect the moment when SEFI occurs. Test setup was developed on the basis of National Instruments PXI modular equipment and LabVIEW software. Developed fault injection system was tested on PIC17 microcontroller. The comparison between...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
Security is a major issue nowadays for the embedded systems community. Untrustworthy authorities may use a wide range of attacks in order to retrieve critical information. This paper introduces ARMHEx, a practical solution targeting DIFT (Dynamic Information Flow Tracking) on ARM-based SoCs (e.g. Xilinx Zynq). Current DIFT implementations suffer from two major drawbacks. First, recovering required...
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW...
Flash memory-based storages are used in a wide range of systems from small mobile devices to large-scale system servers. The performance demand from applications and the technology of flash memory vary widely from one system to another, making it difficult to design a universal flash memory scheduler for all systems. In this paper, we present a framework for efficient and flexible flash memory scheduling...
Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some...
The Simon Cipher is a low complexity, symmetric cipher that was designed for pervasive computing applications, such as radio-frequency identification (RFID) and Internet of Things; however, there has not been a hardware implementation of the Simon Cipher that addresses the unique low-power and low-device count demands for RFID. We present a bit-serial hardware implementation guide and the simontool...
Effective software defences against errors created by fault attacks need to anticipate the probable error response of the target micro-controller. The range of errors and their probability of occurrence is referred to as the Fault Model. Software defences are necessarily a compromise between the impact of an error, its likelihood of occurrence, and the cost of the defence in terms of code size and...
This paper discourse about a low area elliptical curve cryptographic processor with high performance is implemented. The architecture proposed comprises of a full precision multiplier with two staged segmented pipelining to lessen the clock cycles used by avoiding data dependency. The multiplier uses a modified Montgomery algorithm for point multiplication. The simulation results are obtained using...
In this paper, we present a practical power-analysisbased attack on KCipher-2 software implemented on microcontrollers. The key idea of the proposed attack is to exploit aspecific Hamming weight (HW) leakage from low-end microcontrollers or to skip a specific part of the software sequence by a fault injection on low-end microcontrollers in addition toa conventional power analysis available for KCipher-2...
The use of virtual devices in place of physical hardware is increasing in activities such as design, testing and debugging. Yet virtual devices are simply software applications, and like all software they are prone to faults. A full system simulator (FSS), is a class of virtual machine that includes a large set of virtual devices – enough to run the full target software stack. Defects in an FSS virtual...
Future IoT systems are tightly constraint by cost and size and will often be operated from an energy harvester's output. Since these batteryless systems operate on intermittent energy they have to be able to retain their state during the power outages in order to guarantee computation progress. Due to the lack of large energy buffers the state needs to be saved quickly using residual energy only....
Programmable Virtual Networks (PVNs) make the network more flexible and allow the fast introduction of new services. However, several shortcomings hamper their wider adoption, including: (i) the extensive knowledge required to configure and manage the NetApps, (ii) the lack of descriptors to detail all nuances of the NetApps, and (iii) there is no solution that enables to distribute and configure...
An ideal solution for soft error tolerance should hide the effect of soft errors from user and provide correct results at expected time. Software solutions are attractive because they can provide flexible reliability without imposing any hardware modifications. Our investigation of state-of-the-art error recovery techniques reveals that they suffer from poor coverage (ability to detect and correctly...
In the past decade, the number of reported security attacks exploiting unchecked input firmware values has been on the rise. To address this concerning trend, this work proposes a novel detection framework, called DOVE, capable of identifying unlikely firmware execution flows, specifically those that may reveal a security vulnerability. The DOVE framework operates by leveraging a symbolic simulation...
Chip level Functional verification of processor based IC designs predominantly use directed test cases implemented in high level programming languages like "C". The verification test case software (SW) runs on the control core of the IC and configures different IPs to implement a particular functionality that verifies a set of functional requirements. Chip level verification environment...
Dynamic checking the integrity of software at run-time is always a hot and difficult spot for trusted computing. In this paper we present a lightweight approach, Control-flow checking using branch sequence signatures (CFCBS), to checking violation of control flow integrity at run-time. Our solution assigns a unique branch sequence signature, which enhances the capability of fault coverage, to each...
The integration of mixed signal circuits in Systems on Chip is a trend in modern systems and applications with important challenges. In particular, the simulation of this kind of systems is a very time-consuming process that is becoming more and more complex due to the size of current designs. This paper describes a HW/SW co-simulation environment for mixed-signal circuits. The analog components are...
A brief review of Protected Execution Mode (PEM) for user-space applications featured in Elbrus architecture is described first. Then, AddressSanitizer, a well-known utility by Google Inc, is considered as an example of a pure software technique of memory control. Comparative analysis of these solutions is given with performance flaws, applicability and boundary violation detection quality.
An unconventional software testing method, fault injection based on fault model, is enhanced to improve the software reliability testing and measurements. Dynamic fault models for injecting faults through software are investigated and reported in this paper including memory faults, CPU faults and communication fault models. Dynamic fault models can be used to simulate influences which are caused by...
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