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Packages of commercial Gallium-Nitride power semiconductors present increasingly small dimensions to enable low parasitic inductance, increasing the heat flux density of the package and the challenges associated with their thermal management. This paper compares between Printed Circuit Boards and Direct Copper Bonded as substrates for a Gallium Nitride based half-bridge from a thermal and reliability...
In this paper, the growth behavior of twin boundary in plated copper film was thoroughly investigated using SEM and TEM to facilitate its application as under bump metallization (UBM). The bath consisting of different amounts of H2SO4 was adopted to individually study the influence of pH on cross-sectional microstructure of copper film. Increasing the sulfuric acid concentration could greatly increase...
As the electronic packaging density continues to increase, flip chip or stacked packaging via bump bonding is gradually replacing traditional wire bonding and will become the mainstream packaging form in the future. For copper bumps, this new type of electronic interconnection has not yet been fixed by industry standards. Therefore, this paper has made a preliminary study on the reliability of this...
A new DBC-based hybrid packaging and integration method is proposed in this paper. A multilayer power module is formed by a direct-bond-copper (DBC) and a window cutting printed circuit board (PCB). The SiC chips and PCB are placed and soldering on the DBC. Al bonding wires are used for connecting the chips and the PCB. A full SiC half-bridge power module is designed and fabricated in compact size...
This analysis focuses on two of the primary variations of fan-out wafer level packaging: die-first packaging in which the die are placed face down, and die-last packaging. These two technologies share many of the same activities, but those activities occur in a different order. One key factor setting these two process flows apart is yield. Even with the assumption that the same level of defects are...
To take full advantage of silicon carbide (SiC) devices' superior electrical and thermal performance, advanced power module packaging designs and suitable materials are required. In this paper, the development of a new high power density module using the Power Overlay (POL) packaging platform is presented. The wirebond-less packaging platform has shown significantly reduced electrical parasitics,...
In this study dry film photoresist material is employed to fabricate thicker Cu pillars and solder interconnects. The development of the dry film photoresist process for forming 200 µm thick copper pillar were introduced. Several experiments were conducted to find the optimized process parameters for the dry film photoresist. A Laminator was adopted to laminate the dry film. The lamination temperature...
Emerging fan-out packages require advances in mold compounds, polymer interfaces to metals and silicon, and innovative processing to reach the required high reliability. In this paper, we discuss the fracture energy for mold compound interface to copper and silicon, and use that information for studying interfacial delamination propagation of mold compound. We have examined mold compound delamination...
Laminate chip embedding tailored to very thin dies is an attractive package technology for the integration of logic and power dies. In this paper we report on a new leadframe based laminate chip embedding technology. Best benefit from this technology can only be achieved if experience from silicon front-end, assembly and packaging, as well as from printed circuit board research is combined and consequently...
We have developed a novel packaging tool-set of 13 machines to support continuous manufacturing process from a half-inch wafer process line until ready to be used. The packaging tools are made under minimal fab standard so that a half-inch wafer can be attached on a metal-substrate without dicing. The method that we employed is a BGA (Ball Grid Array)-type solder array which consists of following...
A novel nanocopper-based packaging material was developed for robust, void-free thermal interfaces between LEDs and heat sinks/spreaders. It is applicable to other high power components and devices allowing sub-10 micron thermal interfaces to enable high heat transfer rates. Other applications are in TSV & wafer level packaging, embedded chip packaging, direct print of Si and Glass interposers,...
Three dimensional integrated package constructions are a very active area of development in the electronics packaging industry. In many of these constructions, creating vertical interconnections between packaging elements presents a particular challenge. This problem is exacerbated as package footprints and pitches become smaller and exacting interconnection height is needed to accommodate nested...
There is no doubt that component embedding technology becomes more visible in handheld applications like smart phones and wearables. Embedding technology is pushing the miniaturization which is a must for the next big wave of Wearable Electronics and Internet of Things (IoT). The technology is going to System in Package and the question today is how far you can go in miniaturization and how much of...
Soldering of packaged electronic components using industry standard Sn-Ag-Cu (SAC) lead-free solders on low-cost foils, which are often the substrate of choice for flexible electronics, is challenging. This is mainly originating from the fact that the reflow temperatures of these solder alloys are normally higher than the maximum processing temperature of the low-cost flex foils. To enable component...
Contact resistance of the micro bumps in a PBGA (Plastic Ball Grid Array) packaging with TSV (Through Silicon Via) structure was characterized in this study. To this end, a self-designed TSV daisy chain circuit was proposed as the measurement paths and the test samples were made with commercialized packaging process to simulate real product behavers. Based on circuit model analysis, contact resistance...
As the demand expanding for high electrical performance, high pin count and low cost, the copper pillar bump packaging has been extensively used in recent years. However, the drawback is that copper pillar bump can introduce high stress, especially on low-k chip. In this paper, finite element method was adopted to optimize the structure of copper pillar bump, aiming at relieving the stress of low-k...
As the advancement of transistor nodes faces unprecedented challenges and work continues to extend Moore's law at the back end of the line (BEOL), packaging has become one of the fastest growing segments in the semiconductor industry. Lead-free soldering is one of the most critical steps in interconnection at the packaging level. The evolution of packaging requirements for various devices is driving...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring...
This paper presents Thick Printed Copper (TPC) as substrate technology for High Brightness LEDs, which features a strongly improved reliability combined with a significant cost advantage over incumbent technologies for High Brightness LED substrates. The advantages of TPC over Direct Bonded Copper (DBC) and Direct Plated Copper (DPC) substrates will be demonstrated by thermal shock test results and...
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