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An integrated reset controller (voltage supervisor) is designed and implemented. The system generates a reset signal, active while power supply brownout conditions are detected and for 250 ms after the supply voltage has increased to acceptable levels. The circuit is built in a Deep N-Well (DNW) 5V 0.35μm CMOS process, which provides good isolation between the on-chip devices and the substrate. The...
Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs...
We present a new bonding process for gallium nitride (AlGaN/GaN) devices from Si onto diamond substrates. In our technology AlGaN/GaN-devices are transferred from silicon (Si) onto single (SCD) and polycrystalline diamond (PCD) substrates by van der Waals bonding. Load-pull measurements on Si and sCd at 3 GHz and 50 V drain bias show comparable power-added-efficiency (PAE) and output power (Pout)...
Lateral GaN-on-Si HEMT technology enables integrated high-voltage half-bridges with gate drivers. However, the capacitive coupling through a common conductive substrate influences switching characteristics. The measured hard-switching turn-on time with floating substrate increased to over 16 ns as compared to conventional source-connected substrate (1 ns), switching 300 V/4A with GaN ICs comprising...
GaN emitters have historically been of hexagonal phase due to natural crystallization. Here we introduce a cubic phase GaN emitter technology that is polarization-free via cointegration on cheap and scalable CMOS-compatible Si(100) substrate.
A 6-layer continuous and uniform MoS2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS2 transistor are investigated, and enhanced carrier mobility (0.69...
This work proposes a new method for the extraction of the flatband voltage, effective nanowire width and doping concentration of junctionless nanowire transistors. The accurate extraction of such parameters is essential for the understating of the device behavior and for the prediction of its performance in circuits through analytical models. The method is validated using 3D numerical simulations...
As beta-phase gallium oxide is gaining attention for potential application in electronic and optoelectronic devices, this paper addresses techniques for nanowire fabrication that offer the potential for low cost simplicity with the uniformity and reproducibility that are necessary for useful device implementation of these nanowires.
The mass production of secure circuits demands nowadays new testing methods able to detect the possible existence of hardware Trojans, which might be even a slight layout alteration. This paper proposes a new method for the detection of Trojans by exploiting preexisting current sensors that are originally built in system's subcircuits as online-testing devices for detecting radiation- or laser-induced...
This paper describes the design of the transceiver, which is the implementation of the physical layer of EIA/TIA-485 standard. This circuit is a part of a more complex System on Chip designed in 130 nm CMOS technology. The problems encountered during the design process was described. The crucial issue was the relatively high voltage range, from −7 V to 12 V, that may appear on the pins of the SoC...
We report the first monolithic integration of InGaAs channel transistors with lasers on a Si substrate, achieving a milestone in the direction of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers for realizing transistors and lasers were grown epitaxially on the Si substrate using MBE. InGaAs n-FETs with Ion/Ioff ratio of more than 106 and very low off-state...
A 320×240 back-illuminated Time-of-Flight CMOS image sensor with 10μm CAPD pixels has been developed. The back-illuminated (BI) pixel structure maximizes the fill factor, allows for flexible transistor position and makes the light path independent of the metal layer. In addition, the CAPD pixel, which is optimized for high speed modulation, results in 80% modulation contrast at 100MHz modulation frequency.
Layout design principles of IP blocks in the IC, and frequency mixers in particular, are discussed. Several variants of the layout design are carried out. They are modeled and compared to a schematic implementation. Qualitative assessment of implementations is carried out. The conclusions and the ways of improvement are proposed. The nature and the origin of deviations and variations in the process...
Despite the huge market potential of Printed Electronics on Flexible substrates, the printed circuits and systems are yet to be manufacturable due to high cost fabrication processes, large process variations between devices, large and somewhat intractable variations when the devices and their substrates are bent, and lack of a comprehensive Process Development Kit (PDK). In this review paper, we review...
Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor is analyzed by the device simulations. Geometrical parameters of the local p-well substrate, which is used to introduce the second drift region are investigated. It is shown that the length of the p-well lpw=0.5 µm is sufficient to obtain efficient electric field shielding and BVCEO independent of the transistor current gain...
The aim of the research is to develop a material thickness measurement method to monitor oxide polishing by Chemical-Mechanical Planarization (CMP) during the realization of the Shallow Trench Isolation (STI). The underlying goal is to build a statistical regulation model of the polishing time on a single platen (the two others platens are monitored by an endpoint signal). In addition to the process...
In highly-scaled CMOS technologies, analog and digital functionality are often combined into more powerful systems. Implementation of any complex digital circuit requires digital synthesis and therefore a digital standard cell library. Absence of the digital libraries in core design kits provided by the foundries is a significant hurdle for academic institutions to design complex electronic systems...
Symmetric Lateral Bipolar Nano Scale Transistor has emerged as a promising device for future low power digital and mixed signal circuits with application in NEMS. This novel device has shown promising results in terms of Voltage-transfer-characteristics and butterfly curves for digital applications [2, 10]. It has shown better cut-off frequency and gain for low power mixed signals circuits. This paper...
Reliability tests on 600V-rated GaN-based normally-off hybrid-drain-embedded Gate Injection Transistor (HD-GIT) are performed. High-temperature reverse-bias test on HD-GIT reveals that the lifetime is dependent on the leakage current before the reliability test. Acceleration factors for the temperature and reverse bias voltage are extracted. Based on the obtained results, devices are designed so that...
Slowing Moore's law and never-ending system demand for multi-functional integration had set a new stage for “advanced packages”, since 2.5D interposer FCBGA with GPU & HBM successfully developed in 2015. Recently “Fan Out Wafer-level Package” started to be adopted by high-end smart phone AP design, for ultra-thin and excellent interconnect performance. This not only inspires packaging industry,...
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