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High Efficiency Video Coding (HEVC) is the new video compression standard. A novel optimized architecture of Integer Motion Estimation (IME) for HEVC processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 43 fps (frames per second) with a frequency of 142 MHz and a latency of 402 clock cycles. The proposed design has been synthesized and simulated...
Reliability testing has become extremely important in modern electronics as the soft error rate has been increasing due to technology scaling. The testing must be controllable, generic, done before deployment, cheap, and fast. Even though fault injection is often the most appropriate solution considering these requirements, it is very time-consuming. This work proposes a hybrid fault injection framework...
This paper presents a new low complexity architecture of least-mean-square (LMS) adaptive filter using distributed arithmetic (DA). The DA based LMS adaptive filter requires lookup tables (LUTs) for filtering and weight updating operation whose complexities grow exponential with filter order. In the proposed technique, the complexity of LUT for DA based LMS adaptive filter is reduced by two new serial...
The increasing resolutions combined with storage and processing limitations of mobile devices point to the need for new compression techniques for video coding. Meanwhile, to achieve higher compression rates without compromising quality, the coding process becomes more and more complex. In reference software of HEVC the most time consuming step is the execution of Motion Estimation (ME), which is...
In this paper we focus on the issues of hardware implementation of genetic algorithms (GA) in hardware. In their classic implementation, the genetic algorithms search for a global minimum or maximum of a multidimensional function called the fitness function. If the problem, i.e. the fitness function, is too complex for a brute force search, we can look for a solution based on GA. In this situation...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
Fault injection testing approaches assess the reliability of execution environments for critical software. They support the early testing of safety concepts that mitigate the impact of hardware failures on software behavior. The growing use of platform software for embedded systems raises the need to verify safety concepts that execute on top of operating systems and middleware platforms. Current...
The paper suggests very fast electronic solutions for priority buffers that take data from many potential sources, accumulate them in a register, and output the most priority item in run time in such a way that as soon as a new value arrives it is included in the set with all previously received and untreated items and properly handled. It is shown that such circuits are required for real time embedded...
This paper presents the system that allows SEFI modelling by means of injecting upsets in different microcontroller memory blocks, carrying out its functional control and detect the moment when SEFI occurs. Test setup was developed on the basis of National Instruments PXI modular equipment and LabVIEW software. Developed fault injection system was tested on PIC17 microcontroller. The comparison between...
Post Silicon Validation is critical step in order to deliver quality microcontroller chips to customers but is increasingly becoming complex and time consuming process as the design size is increasing. Due to increased number & diversity of design intellectual property, microcontroller post silicon validation has moved towards customized validation concept and hardware setup for individual design...
The increasing use of digital signal processors (DSPs) in wireless communications and signal processing necessitates the optimization of compilers to support special hardware features. In this paper, we propose a compiler transformation method for zero overhead loop (ZOL). It supports very long instruction word (VLIW), internal branches and the loops whose iterative times are known at runtime and...
Over the past few years we have articulated theory that describes ‘encrypted computing’, in which data remains in encrypted form while being worked on inside a processor, by virtue of a modified arithmetic. The last two years have seen research and development on a standards-compliant processor that shows that near-conventional speeds are attainable via this approach. Benchmark performance with the...
In converters possessing multiple distributed controllers the synchronization of and the communication between the various controllers are important topics requiring careful consideration. The controllers should be able to transmit data and commands to each other so that different control modes can be selected, reference values updated, parameters shared and so forth. Synchronization is important...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
Principle of graphic collection system based on PCI9054 and DSP was introduced in order to collect information outside rapidly and instantly in the paper. The telecommunication of collection card and host computer by PCI9054 interface chip was introduced, the logical programmed module was introduced simplified the design of digital logical circuit and implemented the transform of graphics format,...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
Security is a major issue nowadays for the embedded systems community. Untrustworthy authorities may use a wide range of attacks in order to retrieve critical information. This paper introduces ARMHEx, a practical solution targeting DIFT (Dynamic Information Flow Tracking) on ARM-based SoCs (e.g. Xilinx Zynq). Current DIFT implementations suffer from two major drawbacks. First, recovering required...
We introduce PyRTL, a Python embedded hardware design language that helps concisely and precisely describe digital hardware structures. Rather than attempt to infer a good design via HLS, PyRTL provides a wrapper over a well-defined "core" set of primitives in a way that empowers digital hardware design teaching and research. The proposed system takes advantage of the programming language...
In this paper we present a k-means clustering algorithm for the Versat architecture, a small and low power Coarse Grained Reconfigurable Array (CGRA). This algorithm targets ultra low energy devices where using a GPU or FPGA accelerator is out of the question. The Versat architecture has been enhanced with pointer support, the possibility of using the address generators for general purposes, and cumulative...
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